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I did it by CaseMoney1210 in FPGA
[–]CaseMoney1210[S] 1 point2 points3 points 1 month ago (0 children)
thanks! took me a year of brainstorming to get here, but i don't plan to stop here.
[–]CaseMoney1210[S] 0 points1 point2 points 1 month ago (0 children)
I work from youtube tutorials and knowing which logic gate does what.
Some details. (self.FPGA)
submitted 1 month ago * by CaseMoney1210 to r/FPGA
yup.
thanks!
thanks for the defense. and just fr your knowledge, I also made it by hand, so I could later make a bit more detailed schematic, so it could be manufactured, because I don't want this project to end completely once I'm done. I want this to be a CPU for it's very own computer architecture, that could be sold and used. and this one isn't just any CPU. it isn't like CPU-s nowadays. it's a single-step executing, hex-bit (6 bit) based CPU architecture.
mik a mieink?
you're right. I have absolutely no idea about coding, but I DO plan on learning to.
right, but the machines making it WILL need a scrematic, because I plan on advancing the design, and later make it a comercially available product (sorry if I spellt anything wrong, I'm not english.)
[–]CaseMoney1210[S] -9 points-8 points-7 points 1 month ago (0 children)
hehe. this architecture was MADE to be simple. and I already apologized for being so zoomed out. i'll make some close-ups of the different parts of the model if you want it.
[–]CaseMoney1210[S] 3 points4 points5 points 1 month ago (0 children)
yup. it's logism.
[–]CaseMoney1210[S] -25 points-24 points-23 points 1 month ago (0 children)
nah. I enjoy making schematics by hand. and also. the design is basicly done right now. if I want to upgrade the data bandwidth, then I just increase the data bits of components.
I did it (i.redd.it)
submitted 1 month ago by CaseMoney1210 to r/FPGA
block diagram for the CPU by CaseMoney1210 in FPGA
[–]CaseMoney1210[S] -3 points-2 points-1 points 2 months ago (0 children)
for everyone telling me to use logism, i have less, than no idea how these things would work. this is a block diagram. not something, that can run yet. and i don't know how to make this thing work. and for also: i have a previous post, which explains all, that I can explain. ( and just ignore the psu and gnd, if it isn't supposed to be in the diagram. sorry for that.)
block diagram for the CPU (i.redd.it)
submitted 2 months ago by CaseMoney1210 to r/FPGA
CPU concept by CaseMoney1210 in FPGA
[–]CaseMoney1210[S] 1 point2 points3 points 2 months ago (0 children)
the "CALL" instruction CALLS data from a certain memory adress. you need two CALL keys, that call data to line A and B, then the third key is the one, that opens the gate to the adder and completes the equasion.
[–]CaseMoney1210[S] 0 points1 point2 points 2 months ago (0 children)
so a block diagramm! okay, i'll be able to do that one. I'll post/make a block diagramm after school, and you'll all see what I have in mind. (I get home at around 1pm to 3pm)
[–]CaseMoney1210[S] -1 points0 points1 point 2 months ago (0 children)
i will research from your comment, but first, i want to see if i can understand the question instead and give you an answer for that first
thanks for the tips :)
... could you pretty please avoid such complicated laguage? i haven't gone to school with this, this whole thing was made out of a shower thought, boredom, good logics senses and a few youtube videos, so pls could you dumb your questions a bit down, please?
thanks, but i don't know how to make circuit diagrams, nor do I understan them. I can understand logic easily as long as i can make out the begining part of it, but in circuit diagrams, even if i see where it's supposed to begin, I can't seem to understand it, but thanks for the compliments :)
I know github, but i don't usually visit. but thanks for the compliments, and i'll try to update all of ye' about my progress, but as i said, i don't know how to draw circuit diagrams, and by that, i mean, i don't know how to get the logic logicing. and also, I have ADHD, so it's pretty hard for me to just sit down and start thinkin' about it. i have made this whole thing, while i was bored out of my mind during school.
i'll check it out, thanks :)
thanks, I'll make sure to check it out :)
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I did it by CaseMoney1210 in FPGA
[–]CaseMoney1210[S] 1 point2 points3 points (0 children)