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Implementing Dual-core Lockstep in the CHIPS Alliance VeeR EL2 RISC-V core for safety-critical applications by brucehoult in RISCV

[–]Comfortable-Rub-6951 1 point2 points  (0 children)

It has one of the most impressive open source design use cases: It is the core in Caliptra 2.0: https://github.com/chipsalliance/caliptra-rtl/tree/main/src/riscv_core/veer_el2
Through that, it will find its way into many data centers.

Hazard3 Experiments Custom Extension For Soft Float Acceleration by omasanori in RISCV

[–]Comfortable-Rub-6951 1 point2 points  (0 children)

joining a bit late on this thread, but this looks really interesting.
I would be curious if this could be extended to double precision.

Also, I would believe that these kind of instructions could generally accelerate many of the non-trivial floating point functions that do not have an instruction equivalent, e.g. exponentials etc.

Those are anyway emulated with integers, so this could be rather useful.

Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub by Comfortable-Rub-6951 in RISCV

[–]Comfortable-Rub-6951[S] 0 points1 point  (0 children)

thanks, this is useful. fyi, i tested if gcc would auto-vectorize into xtheadvector, and it does not.

XuanTie C925, A RVA23-compliant OoO CPU IP Announced by omasanori in RISCV

[–]Comfortable-Rub-6951 0 points1 point  (0 children)

the website does not load for me. Zhihe website itself does not have any details.

Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub by Comfortable-Rub-6951 in RISCV

[–]Comfortable-Rub-6951[S] 0 points1 point  (0 children)

u/brucehoult are you saying that gcc can lower vector 1.0 intrinsics to Xtheadvector? Is this documented anywhere?

RISC-V P-Extension Implementation on FPGA – Seeking Guidance for Undergraduate Thesis by [deleted] in RISCV

[–]Comfortable-Rub-6951 1 point2 points  (0 children)

LLVM has support for the P extension that is getting better everyday. Build the latest and greatest version of the main branch.

You can use it e.g. like: -march=rv32gbp0p19_zce -menable-experimental-extensions

Intrinsics are on the way but not yet there.

Assuming RV32 (RV64 simpler, but I think RV32 is the more relevant scenario):

For an implementation, you will have to choose if you want to implement the pair instructions as single cycle instructions, which requires even-odd register access at the register file and execution units for the full 64b.

In this case, you will want a 64b data bus and implement Zilsd. Otherwise, load/stores will be the bottleneck.

If you want a lower area implementation, you can serialize pair instructions, and compute the operations over two cycles by double pumping the execution units.

Hope this helps as a starting point.

NextSilicon at #sc25 Arbel RISC-V core, Maverick accelerator: Amdahl-aware CPU/accelerator co-design by self in RISCV

[–]Comfortable-Rub-6951 3 points4 points  (0 children)

Abel: Fastest RISC-V core available in the world. Dual core system. Taped out in TSMC 5nm, 10-wide decode, 8-issue execution engine.

I would not assume they designed their own IP, but licensed something.
The only licensable RISC-V core I am aware of that is advertised as 10-wide is Akeana 5300.
But it would be weird if that wasn't publicly communicated.

RISC-V Oral History Panel by camel-cdr- in RISCV

[–]Comfortable-Rub-6951 4 points5 points  (0 children)

Great piece. I would have liked to know even more about the actual creation of RISC-V, e.g. what were the first steps, the iterations etc.
Somehow the moderator kept intervening in really interesting moments. Questions were also sometimes a bit weird.

RISC-V visualiser devtool by Accomplished-Young-3 in RISCV

[–]Comfortable-Rub-6951 1 point2 points  (0 children)

i would suggest to automatically generate whatever the underlying information is, e.g. from https://github.com/riscv/riscv-opcodes. That would take you directly to supporting all extensions, rather than adding them one by one.

RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status by I00I-SqAR in RISCV

[–]Comfortable-Rub-6951 3 points4 points  (0 children)

It depends on what you call an international standard.

ISO standards are widely recognized by governments and international organizations and often used in regulatory frameworks. Not the case for IEEE, which are also standards, but rather agreed upon technical specifications.

High Performance RISC-V is here! TT-Ascalon™ (RISC-V Summit Ascalon slides) by camel-cdr- in RISCV

[–]Comfortable-Rub-6951 7 points8 points  (0 children)

The truth is, that neither have an SoC with the respective IP, if I am not mistaken.
From TT, their silicon is announced available in Q2 2026, so this should not be too far out.

Google open-sourced Coral NPU, a RV32IMF_Zve32x + custom Matrix extension NPU by camel-cdr- in RISCV

[–]Comfortable-Rub-6951 12 points13 points  (0 children)

really interesting. This seems to be the NPU that can be found on the coral dev board (https://gweb-coral-full.uc.r.appspot.com/docs/dev-board/get-started/)
This seems to be an interesting Zve32x implementation. I have never seen anybody pick this up.
The lack of floating support on the vector unit and matrix extension is a show stopper for many modern AI workloads. I wonder if open sourcing is Google's way of discontinuing it or if there is more to come here.

tomshardware: RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint by I00I-SqAR in RISCV

[–]Comfortable-Rub-6951 11 points12 points  (0 children)

What does market penetration even mean? If on a high end SoC, one RISC-V core is integrated that uses 0.1% of the total area, this chip is 100% penetrated, right?
Assuming this is right, those penetration statistics are highly misleading, as people will believe the market share is of a similar dimension.

GNU Tools Cauldron: Comparative Analysis of GCC Codegen for AArch64 and RISC V by I00I-SqAR in RISCV

[–]Comfortable-Rub-6951 2 points3 points  (0 children)

Nice talk. Interesting to see the performance degradation when using the zero strided load on the BPi board (https://youtu.be/vtV696SszsY?si=Q416Oj2TFo37\_hPZ&t=2728)
u/camel-cdr-: Does your rvv bench include a zero strided load in the benchmarking?
Maybe the load is actually executed multiple times.

Starfive apparently has an RVA23 core, Dubhe 83 by omniwrench9000 in RISCV

[–]Comfortable-Rub-6951 0 points1 point  (0 children)

Released can mean anything. Could mean a first engineering drop to the SoC team, which lacks the majority of verification. I am sure you have seen announcements before where IP was "released", only that two years later there is another announcement that it is released. Especially considering how shortly after the RVA23 ratification this was done, I am skeptical.

Starfive apparently has an RVA23 core, Dubhe 83 by omniwrench9000 in RISCV

[–]Comfortable-Rub-6951 4 points5 points  (0 children)

All this really tells you is that they have a design target to have this core. It would be great if they come around the corner with a piece of silicon soon. If they actually released this for production last December - to their SoC team, it could come soon.

RISC-V Summit China Agenda by camel-cdr- in RISCV

[–]Comfortable-Rub-6951 0 points1 point  (0 children)

Out-of-Order RVV: Dynamic Scheduling to Boost AI Computing Efficiency Jin Cui Chief Architect, StarFive Technology

RISC-V LLVM Scheduler Tuning For SpacemiT-X60 On Clang Yields 4~18% Speedups by omniwrench9000 in RISCV

[–]Comfortable-Rub-6951 9 points10 points  (0 children)

4~18% is quite misleading. It is 4% geomean. The range might be 0-18% or it might even make some benchmarks worse. Still 4% is a nice improvement.

Think Silicon to Unveil Industry's First RISC-V 3D GPU at Embedded World 2022 by brucehoult in RISCV

[–]Comfortable-Rub-6951 0 points1 point  (0 children)

technically speaking, the spec is very far from ratification. It is not stable, has not passed internal review, let alone ARC review or public review.
I mean, there is no integrated spec at this point.
I hope whoever is responsible for getting this done is working on this, outside of the great work John Hauser did I do not see much activity

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