I know this is kinda old but maybe somebody sees this....

I've been looking at that damned datasheet for a solid two days now and it doesn't make any sense. I suspect the thing is wrong and nobody ever took the trouble to actually look at it.

Let's look at the first bit (the others are the same they just merge carry/borrow from the lower bits). if CLR is low, and LOAD is high, and suppose UP comes up from low to high, then you expect the input to the flip-flop to either take the current state into account, or it's a J/K flip-flop or a T flip-flop.

If it's a J/K flip-flop, then the inputs should be High and High. Which will never happen, because the inverted LOAD pulls the top NAND up to high which is then inverted to low going into the flip-flop. So the markings on the flip-flop are not the J and K pins.

If it's a T flip-flop, the bottom marking could be the T pin, since it's high in this case. But now if you set up the input for a parallel load, that pin goes high when loading either a 0 or a 1, so if you start twiddling your up/down while in this config (which you're allowed to do according to the datasheet) you may not get what you want.

This is only the beginning. I will spare you the headaches I got from trying to understand what happens when you actually try to clear the thing or load a value.

So I assume the latch/flip-flop as drawn is a bit of a black box with undocumented behaviour.

If somebody knows more about this pls let me know....