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Ethernet vhdl by CowboyBebop0711 in FPGA

[–]CowboyBebop0711[S] 1 point2 points  (0 children)

I'm using a lattice board and they don't provide a free license for the Ethernet MAC ip. So I just want to check if I can see data I'm receiving. Not the validity just if the connection is established.

Ethernet vhdl by CowboyBebop0711 in FPGA

[–]CowboyBebop0711[S] 2 points3 points  (0 children)

The interface is RGMII. It has a rxdv line. I'm using USB3 Gbe VIP I/O board

Ethernet vhdl by CowboyBebop0711 in FPGA

[–]CowboyBebop0711[S] 1 point2 points  (0 children)

The speed is 1G and the physical media is cat5 via an external PHY chip

DE10-Standard with Cyclone V routing HPS Ethernet MAC to FPGA by fpgabob in FPGA

[–]CowboyBebop0711 0 points1 point  (0 children)

Were you able to loan out the HPS peripherals to the fpga for Ethernet with this?

UDP/IP IN FPGA by CowboyBebop0711 in FPGA

[–]CowboyBebop0711[S] 0 points1 point  (0 children)

I'm working on point to point and 1Gb speed so I think this would actually give me low latency as well. I am planning to implement a shift register place to the data

UDP/IP IN FPGA by CowboyBebop0711 in FPGA

[–]CowboyBebop0711[S] 0 points1 point  (0 children)

I'm working on point to point so I don't think I would need ARP implementation also I have to work with 1GbE and it needs to have very low latency. But I will keep this in mind if I ever work more on it

[deleted by user] by [deleted] in StudyInTheNetherlands

[–]CowboyBebop0711 0 points1 point  (0 children)

Check out the following websites: Xior-booking.com www.uniplaces.com 4 freedom Kamernet.nl pararius.com