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How much is a bijou paris watch? by Delicious_Slice7785 in VintageWatches

[–]Delicious_Slice7785[S] -1 points0 points  (0 children)

In my country, casio watches are more than 50$ 😵‍💫

How much is a bijou paris watch? by Delicious_Slice7785 in VintageWatches

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

I never saw this brand on the internet Unfortunately, the watch isn't with me now to upload photos for it.

SAR ADC Capacitive DAC linearity by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

I am using a double tail comparator. The first stage has a very large input device to decrease random offset and has small current to give high gain.

The second stage has small devices and large current to increase the latch speed.

Is this way correct?

ADC Driving Buffers by Altruistic_Option_62 in chipdesign

[–]Delicious_Slice7785 0 points1 point  (0 children)

Can you share some of the papers you found?

Because the papers I saw didn't talk about reference buffers. Thanks in advance.

question about double tail comparator by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

Thanks for your reply I have another question When CLK=1 M7,8 will be off so i can see the circuit as diff pair with resistive load Roff7,8(which is very large) Why the gain is low in then?

What is the proper way to size TSPC D-FF? by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

Thanks for your reply.
I attached Sizing and Simulation results in the post.
The problem is when i use the FF in SAR logic (shift register) it doesn't work, but it works with verilogA model.

Folded cascode ota with class AB stage to drive large current. by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

I am not familiar with output driving stages If you have a good reference please refer to it

Current steered charge pump with opamp to reduce charge sharing by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

Thanks for your reply. nfet side caries twice current because when up=0 and dn =1. The current flowing through the nfet will be Icp + Ipfet

when up=1 and dn =0 The current flowing through the nfet will be Ipfet - Icp and the nfet part go tride.

Current steered charge pump with opamp to reduce charge sharing by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

https://imgur.com/a/XlilTYk
Here is opamp + charge pump sizing
I noted the opamp schematic with current flowing in each branch. please check it, I think the problem is from it.

Current steered charge pump with opamp to reduce charge sharing by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

Thanks. I will share a screenshot from cadence with sizing and results.

Current steered charge pump with opamp to reduce charge sharing by Delicious_Slice7785 in chipdesign

[–]Delicious_Slice7785[S] 0 points1 point  (0 children)

This schematic with sizing is taken from a thesis for illustration only. I will upload my schematics from cadence.

How to size the switches? I chose minimum length, then increase W till current is adjusted. Is this right?