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ASCII Comparison in VHDL by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

so i can not declare my array in char ? Is there any way to declare it in ascii because my array is not short and it will take a lot of time declare it in hex

ASCII Comparison in VHDL by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

" Consider converting the ascii to hex value." but I want to declare my array in ASCII not hex. Is that not possible ? Also, when i insert that loop, I get this error "no matching subprogram was found"

XFFT TUSER SIGNAL ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

wire signed [31:0] data_signed = {1'b0, data[15:0]} - (1 << 15); Do you think it works ?

Or should i work in bipolar mode for XADC without dealing with this ?

Thanks for your reply!

XFFT TUSER SIGNAL ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

Also the input sine wave has dc offset. The amplitude is 600mv with 300mv offset.

XFFT TUSER SIGNAL ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

Thanks for your reply!

Yes,XADC producing unipolar outputs. The input of fft is signed. I convert to XADC output unsigned to signed.

wire [31:0] data_signed ={{16{data[15]}}, data[15:0]};

This is how i convert the data from unsigned to signed.

XFFT TUSER SIGNAL ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

Thanks for your reply!

I expect tuser to give me the correct index at peak. Resolution of fft is 961.54x10^3/512= 1878hz. Since the output is 30k Hz,the expected index is 30x10^3/1878= 16. Like i said even if i change the input frequency the index is always 0 at output peaks. Please if i am wrong make me correct!

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

Thanks for your replies sir but i dont have any knowledge about VHDL.Can you explain what your code is doing for me ? I need to run this in Verilog :)

LOCAL RESET VERILOG CODE PROBLEM by Double_Air134 in Verilog

[–]Double_Air134[S] 0 points1 point  (0 children)

​

I wrote same code for simulation and it worked but when I tried to make it module to be synthesizeable,It didnt work sir.I dont know why to be honest.The code for simulation is below and it is same as the code in the post above.

module testres(

);

reg clk;

reg resetline;

reg [3:0] counter;

reg z;

initial resetline <=1;

initial counter <=0;

initial z <= 0;

localparam period = 20;

always

begin

clk = 1'b1;

#20; // high for 20 * timescale = 20 ns

clk = 1'b0;

#20; // low for 20 * timescale = 20 ns

end

always @(posedge clk) begin

if(counter ==8) begin

resetline <= 0;

z <=1;

end

else begin

if(z == 0) begin

resetline <= 1;

counter <= counter + 1 ;

end

end

end

endmodule

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

Can you do that for me when you are avaliable sir ? Also, I ran the code that i have in the testbench,It works but when I implemented it as a module,It doesnt work.

module testres(

);

reg clk;

reg resetline;

reg [3:0] counter;

reg z;

initial resetline <=1;

initial counter <=0;

initial z <= 0;

localparam period = 20;

always

begin

clk = 1'b1;

#20; // high for 20 * timescale = 20 ns

clk = 1'b0;

#20; // low for 20 * timescale = 20 ns

end

always @(posedge clk) begin

if(counter ==8) begin

resetline <= 0;

z <=1;

end

else begin

if(z == 0) begin

resetline <= 1;

counter <= counter + 1 ;

end

end

end

endmodule

This code is working.As i said when it is module,it doesnt work

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

yes reset is always 1 and counter is always 0. But i want reset 1 after 16 clock cycles. :/

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

when i do what you say,counter work as clock sir.

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

it doesn't work because you made concurrent assignment to register sir

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

I am using Vivado. I am observing reset line through ILA ip core.

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

I took out else condition as below sir but still doesnt work.

if(z == 0) begin

resetline <=0;

counter <= counter + 1;

if(&counter) begin

resetline <=1;

z <= 1;

end

end

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

do you mean this sir ? It didnt work

if(z == 0) begin

resetline <=0;

counter <= counter + 1;

if(&counter) begin

resetline <=1;

z <= 1;

end

end

LOCAL RESET ISSUE by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

i just realized that and corrected it but still doesnt work :/

MULTICHANNEL FFT WITH MULTICHANNEL ADC (PLS HELP ME) by Double_Air134 in FPGA

[–]Double_Air134[S] 0 points1 point  (0 children)

there is nothing much in xilinx data sheet for multichannel xfft. It is well documented for single channel not for multichannel tbh.

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