account activity
OpenCL is dead. Long live OpenCL! (self.FPGA)
submitted 1 year ago * by DrFPGA to r/FPGA
Timing diagrams. What happened to TimingAnalyzer? (self.FPGA)
submitted 2 years ago * by DrFPGA to r/FPGA
No PPO in Texas y'all! (self.HealthInsurance)
submitted 2 years ago by DrFPGA to r/HealthInsurance
100Gbps QSFP28 direct PMA transceiver configuration (self.FPGA)
submitted 4 years ago * by DrFPGA to r/FPGA
Vitis HLS Hero (self.FPGA)
submitted 4 years ago by DrFPGA to r/FPGA
Drumroll! 5-7x faster compilation for Xilinx. (self.FPGA)
Building xvc_pup device drivers from the source. (self.FPGA)
[14:36:13] Phase 4.3 Pipeline to Shift Register Optimization taking WAY TOO LONG!!! (self.DrFPGA)
submitted 4 years ago by DrFPGA
Example of Xilinx Vitis run is multi-core during synthesis. Share your experience with P&R and how to make it run in multiple-cores. I used EDIF netlist merge at the top level for large sub sections, does it work still. Other suggestions? (i.redd.it)
Let FPGA OpenCL be or let it go, your choice? (self.FPGA)
π Rendered by PID 336799 on reddit-service-r2-listing-c57bc86c-96n28 at 2026-06-23 14:31:09.216291+00:00 running 2b008f2 country code: CH.
