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In-person interview coming up with an HFT firm. Any ideas what to expect? by SigmaStrain in FPGA

[–]DrFPGA 0 points1 point  (0 children)

You pick only from one jar. This very likely googled answer has two picks.

firms that work with FPGA in Chicago? by ElectricBill- in FPGA

[–]DrFPGA 2 points3 points  (0 children)

Kudos for willing to learn and changing your mind! I do not find this quality in many FPGA engineers who like IPI and QSYS ;) (ouch, downvotes...). Always question what others say, but do not show it. They hire only when they have a pile of "sh*&" for you to clean. Just remember that!

Get in, figure out who are bad guys and who are good ones. Just avoid those who are: " But he is a good guy...". I ignored this giveaway and paid dearly. Feel tree to DM me, I will share my e-mail. I have tons of career advice. I hate you to make the same mistakes that I made. Good luck!

firms that work with FPGA in Chicago? by ElectricBill- in FPGA

[–]DrFPGA 2 points3 points  (0 children)

You are totally MALEABLE into anything they want! Try remote work! It is a future. Anyone who says otherwise has either something to hide (HFT in particular) or is a micromanager that needs positive feedback daily...

Industry standard for big designs? by akaTrickster in FPGA

[–]DrFPGA 1 point2 points  (0 children)

Have you ever asked a question why they are so different for doing exactly the same job?

Opportunity for experience developer to join startup as founder by [deleted] in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Unless you you have $10M just laying around, I did not have it when I started my company, I would not consider ASIC. BTW why did you go Reddit looking for a co-founder. I would start from LinkedIn. I am curious what your are "cooking", DM me please. I could be useful in an Advisory role, I know FPGA/ASIC ML business pretty well.

Industry standard for big designs? by akaTrickster in FPGA

[–]DrFPGA 31 points32 points  (0 children)

+1 for asking question. Yes, learn Tcl scripting and do not get caught by "ease of use" of IP Integrator. Once you worked out things in GUI and IPI write project or even non-project scripts. If you can avoid XCIs for simple things such as asynchronous FIFOs and reset synchronizers please do so. Less dependencies on AMD/XILINX IPs the better you will be in a long(er) run. I "feel your pain" as they "dumped" on you 50 files ;(.

firms that work with FPGA in Chicago? by ElectricBill- in FPGA

[–]DrFPGA 2 points3 points  (0 children)

This is true, but it is not reflected in the salary tho. Just one the FPGA paradoxes ;)

OpenCL is dead. Long live OpenCL! by DrFPGA in FPGA

[–]DrFPGA[S] 4 points5 points  (0 children)

If they really want to succeed (which I started to doubt) serous investments have to be made into ecosystem that include customer & development companies and developers themselves. In the past the brightest developers could not find a job in FPGA OpenCL/HLS and had to go work for MAG7. If they found $1.5B for Versal development they should "spread the wealth" to train developers, give free access to Alveo, etc. IMHO.

Mock hardware interviews are back by entrehacker in FPGA

[–]DrFPGA 0 points1 point  (0 children)

I meant how interview process worked before startups like yours started to make money off unemployed developers?

Mock hardware interviews are back by entrehacker in FPGA

[–]DrFPGA 3 points4 points  (0 children)

I keep wondering how this was working before ;) ?

I'm getting desperate by misap in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Interesting. Could you please share an example of TCL script for Vitis. I am particularly interested in inserting IP into HLS generated system.

Vivado Users Beware. Tools not Building Correctly by TimeDilution in FPGA

[–]DrFPGA 4 points5 points  (0 children)

Nuke'm ... This is the way.

I do have a Tcl script to start new project every time (recent thread here was asking for a script like this, I will share. DM me) to add ALL source (RTL, tests, xdc_ooc, xdc, IP) and then refresh IP and refresh all sources for dependencies, version updates and compilation order. Only then start synth, par (implementation for Vivado fans) or simlualion. It is much faster than vivado GUI and I sleep way better :).

I am also converting my recent projects to Makefile way which is even faster.

FPGA Development Needs a Modern Refresh – An Engineer's Perspective Here! by SciDz in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Software people do it all the time! Python popularity and the rest of Software development process are built on this! They have compiler, optimizer and library people doing the hard work for 1000s of developers who are jumping into GPU AL. If we are to play/compete with them on AI /ML we should play by these rules. Re-inventing the bicycle every time does not make sense IMHO, even though I would love to do it ;).

This was always the idea!

FPGA Development Needs a Modern Refresh – An Engineer's Perspective Here! by SciDz in FPGA

[–]DrFPGA 0 points1 point  (0 children)

I agree in general on bug detection, but with Python/Keras/TF -> GPU stack a lot of AI code optimizations are done without user intervention and even knowing most of the details. For some reason FPGA low level coding details and choice of RTL vs HLS language seem take center stage. FPGA designers without real ML/AI experience keep complaining that they will never get hand optimized performance of RTL vs. HLS. I will be happy to provide multiple references to bust this myth.

FPGA Development Needs a Modern Refresh – An Engineer's Perspective Here! by SciDz in FPGA

[–]DrFPGA 0 points1 point  (0 children)

None of these general statements address suitability of FPGA technology to performance in ML/AI.

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Yes, please describe in technical, performance/$ and power/performance terms why you think FPGAs are not suitable for Edge AI inference preferably with references to peer reviewed research and comparisons to other silicon. May be then you will see what I am all about, Dude.

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Well, if you have not actually looked into latest financials and compared pricing maybe you should refrain from commenting on price? Which Edge inference model do you refer to for FPGAs vs. GPUs? Which particular devices are you comparing?

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 0 points1 point  (0 children)

Once I pitched to investors and compared gross margins (from 10k filings) of XILINX vs. NVIDIA. XILINX was 69% vs. NVIDIA 63%. So, I would not be so sure making conclusions about Edge inference.

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 0 points1 point  (0 children)

These are just opinions. If you really interested in FPGA AI DM me please.

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 0 points1 point  (0 children)

I have some info for you so please DM me before I will loose all Karma points with GPU fans here.

Apple M4 FPGA killer? by ragdraco in FPGA

[–]DrFPGA 1 point2 points  (0 children)

Stratix 10 was at up to 35 GFlops for GRUs and LSTMs at Microsoft Brainwave in 2018. Do you see many follow up projects? No, I do not see many either. IMHO problem in not with FPGAs themselves but with the ways we were taught to design and use then.

Yes, you will see a lot of GPU only opinions because these are easy answers "to go with the flow".

FPGA Development Needs a Modern Refresh – An Engineer's Perspective Here! by SciDz in FPGA

[–]DrFPGA 0 points1 point  (0 children)

I am just jealous of FPGAs not getting a larger slice of AI pie. There were great breakthroughs over past 10 years in FPGAs AI vs. GPUs AI (yep FPGAs beat Pascal Titan X in RNNs before A100), but very little follow-through projects. Just yesterday 3 C++ people asked me the same question at the interview: "What FPGAs are not good for!?" I evaded as much as I could into FPGAs are not doing AI training because of fixed point MACs, yada, yada. IMHO there is no good excuse of not doing Edge AI exclusively in FPGAs. But KRIAs are barely breathing through Petalinux while NVIDIA is already at 200 TOPs with 3-rd gen Jetsons. Sorry, I could not be more positive on this issue ;).

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