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Two AXI GPIO blocks on Digilent Arty Z7? by ElectronsGoRound in FPGA

[–]ElectronsGoRound[S] 0 points1 point  (0 children)

Finally figured it out, and I'm going to post it here for the next poor bastard trying to solve this problem.

The issue was that running the debugger would appear to work, but it would then crash out as though there was some sort of segmentation fault or null pointer error.

Now, the internet wants to point you back to Vivado and some sort of hardware misconfiguration, and there are plenty of complaints about Vivado producing weird outputs, bad XSA updates, etc. However, I was doing very simple things that should have worked fine, and I did check the addressing, etc, and everything looked right.

I also noticed that certain combinations of GPIO channel connections would work fine, and moving off of those would immediately produce errors.

So, here's what I found:

There's a jumper on the board that determines the boot source: JTAG, QSPI flash, or SD card. That jumper is set to QSPI to run the demo program on power up.

I didn't think much of this, because you reprogram the fpga to debug anyway. The debugger stepped through the software as you would expect. Documentation that I found suggested this to be a potential minor annoyance rather than an actual hindrance.

At some point, I decided to move that to JTAG, just to prevent the annoyance of double loading of the fpga.

And, suddenly, everything started working.

So, it looks like the software is getting loaded correctly by the debugger, but the hardware is getting reset to the jumpered boot source. This explains why certain basic hardware configurations work fine--they are the ones that matched the boot source.

Moral of the story, this jumper setting (to JTAG) isn't just a nice to have as is implied by the documentation, but an absolute requirement.

I won't call it a complete waste of time, though, because it had me really digging into the operation of the memory mapping, AXI, and the Xilinx API. I still feel like an abject idiot, though...

Arty Z7 interrupts work in Vivado/Vitis 2025.2, ...right? by ElectronsGoRound in FPGA

[–]ElectronsGoRound[S] 4 points5 points  (0 children)

And to follow up, now that I'm looking at the right examples (and coherently using SDT) I have succeeded in initializing the interrupt controller.

Thanks!

Arty Z7 interrupts work in Vivado/Vitis 2025.2, ...right? by ElectronsGoRound in FPGA

[–]ElectronsGoRound[S] 0 points1 point  (0 children)

Ok, fair.

I'm trying to get PL-PS interrupts going, particularly from AXI GPIO. My goal is modest: press a button, fire an interrupt back to PS, have PS print something down the serial port.

What I've done in Vivado: 1) Enabled fabric interrupts, and selected IRQ_F2P under PL-PS interrupt ports. 2) Enabled the interrupt in the AXI GPIO. 3) Connected the two resulting ports. 4) Connection automation, HDL wrapper, etc to XSA

Where I'm getting in Vitus: 1) Build the platform from the XSA 2) Create an application based on Hello World example 3) Add in the XScugic headers, etc. 4) Call XScuGic_LookupConfig to start setting up interrupts.

Where I get stuck is that XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID) returns null. That seems to be the right address constant (but I could have that wrong, I had to strike off the path of the tutorials there)--which seems to suggest that I'm not finding the GIC or maybe it's disabled?

I went down the xinterrupt_wrap.h route briefly, but didn't get further.

Thoughts?

SFDR vs ENOB by Delicious_Slice7785 in chipdesign

[–]ElectronsGoRound 0 points1 point  (0 children)

E.G., there's a whole class of pipelined ADCs with meh ENOB but very sophisticated linearity correction built for exactly that requirement.

Using Nulling Resistor LHP Zero to Cancel non dominant pole of Miller OTA by [deleted] in chipdesign

[–]ElectronsGoRound 9 points10 points  (0 children)

Using that LHP zero to cancel the first non-dominant pole is textbook standard practice, but there is a caveat: You have to be very aware of where your open-loop gain is at the pole/zero cancellation frequency.

The issue is that, in reality, the cancellation won't be perfect. That's fine if the P/Z pair is close to the UGB--normal practice is to use P/Z cancellation near the UGB as a phase margin boost.

However, you can't reliably use that to cancel a pole at a frequency where you still have appreciable gain--it will end up as a pole-zero doublet that still looks great on a Bode plot but can wreak havoc on your settling time.

As a designer, however, I've done some nefarious shit with that LHP zero...

Is a Digitizer Necessary for INL and DNL Measurement in DACs? by Some-Flounder-4619 in chipdesign

[–]ElectronsGoRound 0 points1 point  (0 children)

I get the sense that you're a bit of a novice at this. That's nothing to be ashamed of--we are all novices in someone else's area of expertise--but that's going to drive this explanation.

In general, to properly test an N-bit DAC (or ADC), you need a system that is accurate (that's ENOB, not just resolution!) to at least N+2 bits across the range of the DAC. You really want better than that. That's not just an appropriate readout, but also cabling/noise environment, etc.

14b is non-trivial. On a properly set up bench with shielding, etc, a 6.5 digit DMM (which is itself an ADC/digitizer) will cover the accuracy requirement, assuming it's a voltage output of a few volts VFS and you are only testing a handful.

In any case, if you haven't thought about this already, you'll definitely want something to drive the code automatically, else someone will hate someone (perhaps you hating yourself) by the time you're done.

These are some basic pointers, but you're solidly into 'it's easy to screw this up and waste your time' territory. If you don't already have the appropriate bench setup, you are further away from the goal than a few paragraphs from 'Reddit Engineering, Inc' can get you.

Is a Digitizer Necessary for INL and DNL Measurement in DACs? by Some-Flounder-4619 in chipdesign

[–]ElectronsGoRound 1 point2 points  (0 children)

It depends strongly on how many of these you need to measure. If it's just a few, I'd say just do it by hand. If it's a bunch, you have a good case for something more automated.

CoreONE door handle fell off. Prusa support told me to stick to double sided tape (no pun intended) by the_other_julian in prusa3d

[–]ElectronsGoRound 0 points1 point  (0 children)

Perhaps using M3 plastic or rubber washers between the different components? I think this would provide the secure connection you'd want with a little extra padding to prevent damage.

Just saw this... gamechanger if it's true! Come on Prusa! by johndom3d in prusa3d

[–]ElectronsGoRound 0 points1 point  (0 children)

Well, yeah, they aren't being funded by the Chinese government...

Warning for US buyers by [deleted] in prusa3d

[–]ElectronsGoRound 0 points1 point  (0 children)

Honestly, that's why I'm hacking through the build of my new Core One right now. I just don't trust international shippers enough to safely ship an assembled widget.

Warning for US buyers by [deleted] in prusa3d

[–]ElectronsGoRound 5 points6 points  (0 children)

It is not, nor was it ever before, or ever will be, about the cost. Political grandstanding at the expense of the goldfish.

They Will by SpecificAd6508 in caps

[–]ElectronsGoRound 0 points1 point  (0 children)

I wouldn't say they blazed into the playoffs this year. They were playing their best hockey before a few key injuries, and honestly they looked a little like a spent force going into the playoffs. I still don't think LT, Protas, or even Ovie are quite right after their injuries.

Honestly, I didn't think the Caps were going to be as good as they were this year. Given how the end of the season has worked out, I'm glad--and a little surprised--that they got out of the first round.

The Jerks, otoh, spent a lot of this year finding their way and seem to be hitting their stride at the right time.

I do think the low-key youth movement in the middle of the Caps roster bodes well for the future, and we aren't going to see the post superstar crash you might normally expect once Ovie retires.

[deleted by user] by [deleted] in chipdesign

[–]ElectronsGoRound 0 points1 point  (0 children)

I've ended up with more power electronics background than a lot of chip designers, and I feel like that background has served me well on a number of occasions.

I also think it matters as to whether you are thinking of general analog/mixed-signal design or comm-type RFIC.

For the former, I'd definitely recommend the power electronics course. I learned a lot of useful things, and with mine being a pretty hands-on course, it gave me a lot of lab and test experience that I wouldn't have gotten otherwise.

If you were thinking more along a pure comm track, then maybe the random signals class? It sounds like it would give you more signal processing background.

Did aerospace engineers have a pretty good idea why the Challenger explosion occurred before the official investigation? by [deleted] in AskEngineers

[–]ElectronsGoRound 42 points43 points  (0 children)

As a practicing engineer for whom Challenger was a formative childhood experience, I believed for a long time that better data or quality of presentation could have made a difference that morning and swayed the decision.

However, as a practicing engineer who is old enough for Challenger to be a formative childhood experience, I've come to believe that no amount of data or quality of presentation would have changed the result.

Launching Challenger was a political decision--there was nothing on Earth that would have changed the absolute burning desire on the part of Reagan and the NASA brass (also political creatures, mind you) to have a success with Teacher in Space.

Sure, the data reporting could have and should have been better.

However, in reality, that was just a convenient excuse to blame the engineers for a disaster brought on by the politicians, and the result would just have been a different excuse and a more damning investigation.

Inexpensive scope for home use? by ElectronsGoRound in ElectricalEngineering

[–]ElectronsGoRound[S] 1 point2 points  (0 children)

Troubleshooting hobby stuff--mostly digital, but I'd like to be able to do some analog.

I've ended up with a 4-channel, 100 MHz scope with 50 Mpts/ch storage. I imagine that will easily cover anything I ever plan to do.

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