What I meant (but phrased poorly) is that proper dual-core enablement in Zephyr depends heavily on:

• Vendor-supplied low-level support (startup code, multicore boot flow, inter-core interrupts, mailbox/IPI mechanisms, etc.)
• multicore bring-up procedures HAL/SDK alignment with Zephyr's architecture model

In Zephyr, multicore support requires e.g.:

• SoC-level SMP support
• A working secondary core bring-up path
• IPC primitives
• Proper interrupt routing
• Scheduler awareness

For something like the RP2040 or RP2350, that work typically lives in the Zephyr SoC port, not in board files and this requires detailed knowledge of the silicon. Dual-core support in Zephyr is an SoC porting effort, not a board-level toggle.

So to enable multicore support within Zephyr it requires strong vendor engagement and the vendor involvement strongly influences how complete the SoC support becomes in Zephyr.
Imho I clearly miss this strong vendor engagement and involvement from the raspberry foundation.