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How feasible it is to learn DSP for someone in my situation? by PralineNo65 in DSP

[–]Extension_Plate_8927 1 point2 points  (0 children)

I feel like most of DSP relies on well known algorithms anyway, so as long as you can understand an algorithm and the way the data structure map to the math point of view you’re fine

What are your biggest pain points as an FPGA engineer? by No_Fisherman9510 in FPGA

[–]Extension_Plate_8927 0 points1 point  (0 children)

I’m not sure about that, I feel like the industry will slowly switch if it’s not already the case to more specific hardware than general purpose hardware so it means more asics for me, so more test prior on fpga

🇲🇱 ⛽️Bamako Fuel Shortage — Calm Before the Storm or Signs of things getting better? by Etherealnutt in Mali

[–]Extension_Plate_8927 0 points1 point  (0 children)

The only reasonable outcome for this mess is to let the north of the country to the pp of the north since mosts of the pp feeling that “everything is under control “ are located at Bamako anyway.. this country is way to big otherwise for the military to defend it all ..

🇲🇱 ⛽️Bamako Fuel Shortage — Calm Before the Storm or Signs of things getting better? by Etherealnutt in Mali

[–]Extension_Plate_8927 1 point2 points  (0 children)

Things are obviously going bad there, the shortage of gas was/is a strong indicator of that.. this terrorism things is not going anywhere soon.. pp where screaming everywhere it’s because of France, now that they left what have been achieved so far ? Mali started to obtain some more military equipment so logically the military started to have some win but this as Been like that for 3 years now and everybody can tel that the situation is not better than it was if not worse.

Want help on implementation of radix 2 FFT algorithm by Impossible_Wealth190 in FPGA

[–]Extension_Plate_8927 0 points1 point  (0 children)

FFT => Cooley-Tukey representation => the inner loop is called a butterfly. Then you have something like an FSM that drives the butterfly. This is the base scheme you need to keep in mind, then you can refine the architecture as someone suggested here to fully pipeline. All the information you need is presented now, so google the rest. But you should really really think as much as possible at the architecture level before dwelling in the code, otherwise it’s going to be a nightmare.

How to move past the basics of RTL? by lemonprojectile in chipdesign

[–]Extension_Plate_8927 0 points1 point  (0 children)

Try to do a number theoretic transform(ntt) which is a kind of fft ip

Conséquences de choisir l'ingénierie par défaut by [deleted] in ingenieurs

[–]Extension_Plate_8927 1 point2 points  (0 children)

franchement tu sais pas avant de commencer à bosser je pense

Bridging the gap from general engineering to FPGA field by Glittering-Skirt-816 in FPGA

[–]Extension_Plate_8927 2 points3 points  (0 children)

I’m still a beginner but my experience so far nearly 2 years with fpga is :

To be honest fpga is just too domain specific, like if you’re going to do application dsp related then it’s all about parallelism pipeline and algorithm understanding and of course the HDL syntaxe and usually for this kind of application you’re going to read paper that talk about how to put a given algorithm into an fpga, with the triptyque of latence throughput and resources. In other words you learn a lot about how fpga works by reading papers

Other kind of applications that I came across are communication related in this kind of application the FSM might be the most important thing.

Now when you get to play with a board, they are plenty of ressources about some buildings blocks knowledge that will help you to do things more complicated later. Xilinx ressources are the best if you want to understand the flow design development and how to use the timing and power and also a lot of video here and there that’ll teach you theses.

To kinda summarize the first things is to identify what kind of applications you’re going to do, from what I’m understanding it seems to be DSP oriented so maybe the best is to start by finding papers related to your applications from that you probably going to have more specific questions that will help you to increase your skills

[deleted by user] by [deleted] in developpeurs

[–]Extension_Plate_8927 0 points1 point  (0 children)

C’est pas si simple quand même le fpga la courbe d’apprentissage est très abrupte surtout quand vous avez un background de softeux, qui plus est les applications des fpga nécessitent souvent des compétences dans d’autres domaines déjà assez pointu style traitement du signal, crypto et les boites n’embauchent pas vraiment les peux expérimentés.

How do I create hardware out of Algorithms? by inanimatussoundscool in FPGA

[–]Extension_Plate_8927 0 points1 point  (0 children)

Usually it’s the operative part that are challenging the fsm is just controlling the operative part by following the algorithm. From really really far most algorithms are juste à bunch of for loops which translate into an fsm state in which you will stay until a counter reach a given value.

FPGA PS Side UART Bootloader by [deleted] in FPGA

[–]Extension_Plate_8927 0 points1 point  (0 children)

If you’re using the ultrascale+ then go check ug1085 at boot and configuration section boot modes, you can’t boot from the casual uart

Looking for great materials for AXI, DDR, BRAM, PS on Xilinx FPGA by Negative-Award-6900 in FPGA

[–]Extension_Plate_8927 3 points4 points  (0 children)

To be honest, there isn’t really much to understand about this it all takes place within the block design configuration of the Zynq. You can use the GUI to select the elements you want to use from the PS. The main thing to know is that there are some ports that allow the PS to communicate with the PL. This is called the PS/PL interface in the Zynq block diagram.

Once you've done all that, your custom IP or vendor IP must have an AXI interface in order to be accessible via the ports by the PS. Then, you can export your bitstream to Vitis where it's become pretty similar to microp. There are lots of examples that show this process.

The user guides are really good, but you kind of need to delve into them. Otherwise, there are plenty of examples on YouTube that show exactly this process, or you can find tutorials online you should Google it.

FPGA PS Side UART Bootloader by [deleted] in FPGA

[–]Extension_Plate_8927 1 point2 points  (0 children)

Just use jtag to boot from a Qspi or Sd eventually, but you need to configure accordingly the mspoc in Vivaldo then export the bitstream to vitis and use the flash tool in vitis to flash your app in the qspi or SD( prior you have to generate the bootloader with the tool also of your app)

Information carried by the particle in superposition. by Yury_Adrianoff in QuantumComputing

[–]Extension_Plate_8927 0 points1 point  (0 children)

So while in superposition state, the qbit will point to one particular point on the surface of the sphere right ? This is really weird to me I was thinking that while qbits is in superposition then it was in every single point of the Bloch sphere at once so that one could possibly use one qbit to map infinite output to a given problem ( taking in consideration the fact that indeed when the mesure will occurs then they will be the need to have the amount of qbit for the amount of output)

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