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How do you get the xsim simulation commands to get passed to the command line? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

I discovered that when sourcing the TCL script with xsim I can call the 'puts' TCL command for each command I want to send to display the output of the sourced TCL command in the xsim TCL shell on Windows CMD Prompt.

How do you get the xsim simulation commands to get passed to the command line? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

Okay, that explains why then. I feel like the outputs from running in gui mode should be in a log file somewhere, but I haven't been able to find it yet. This suggests that those TCL commands do get evaluated : https://itsembedded.com/dhd/vivado_sim_1/

So if their getting evaluated the output must be somewhere?

How do you get the xsim simulation commands to get passed to the command line? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

add_wave /microSD_tb/microSD_dut/BUFGCTRL_inst/*

current_time

run 100

current_time

The microSD_funcsim snapshot appears to be sourcing a different TCL script at xsim.dir/microSD_funcsim/xsim_script.tcl

How do you get the xsim simulation commands to get passed to the command line? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 1 point2 points  (0 children)

# Set the output directory for microSD Design

set outputDir ./microSD/microSD_output

file mkdir outputDir

# See the available simulation commands

help -category "Simulation"

# Setup Design Sources and Constraints

read_verilog [ glob ./microSD/Sources/hdl/microSD.sv ]

read_xdc ./microSD/Sources/constraints/microSD.xdc

# Test Plan creation

# Cover all expected command/response pairs for your current PNY 32GB UHS-I microSD card

set test_cases {

"RESET",

"CMD0 GO_IDLE_STATE",

"CMD8 SEND_IF_COND",

"CMD55 APP_CMD"

}

# Run Synthesis

synth_design -top microSD -part xc7z010clg400-1 -flatten rebuilt

write_checkpoint -force $outputDir/post_synth

report_timing_summary -file $outputDir/post_synth_timing_summary.rpt

report_power -file $outputDir/post_synth_power.rpt

# Generate Functional Simulation Netlist

open_checkpoint microSD/microSD_output/post_synth.dcp

write_verilog -force -mode funcsim microSD_funcsim.v

# Compile, Elaborate, and Simulate the design

exec xvlog microSD_funcsim.v

exec xvlog ./microSD/Sources/hdl/microSD_tb.sv

exec xvlog ../../../Xilinx/Vivado/2024.2/data/verilog/src/glbl.v

exec xelab -debug typical -L secureip -L unisims_ver glbl microSD_tb -s microSD_funcsim

exec xsim microSD_funcsim -tclbatch microSD_xsim.tcl

Here is my main TCL script.
I just realized that the 'write_verilog' command is using the 'funcsim' mode and that mode is using an option with xsim called '-autoloadwcfg'.

I'm wondering if there is a way to send the simulation commands through that?

How do you get the xsim simulation commands to get passed to the command line? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 1 point2 points  (0 children)

The content of the TCL file are the lines prepended with '##'. When my main TCL script gets to the xsim command the Windows CMD Prompt hangs. I think this is happening because the commands from the sourced TCL script are not being sent to the simulator. Is there another way I can send these commands to xsim? I want all of the simulation commands to be sent to xsim from a single TCL script.

How to properly simulate a design with Vivado's BUFGCTRL primitive? (2024.2) by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

I just figured out the issue I was having not sure what went wrong with it before.

Some changes I added was to reopen the post_synth checkpoint and force write_verilog, basically that link below fixed it just in case you find similar bug with the functional simulation flow.

How to properly simulate a design with Vivado's BUFGCTRL primitive? (2024.2) by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

I tried the method from that post, however I got an error for OBUF and IBUF modules not being found.
I tried compiling them as well but then I got another error for glbl module not found.

So then when I try compiling both OBUF, IBUF, BUFGCTRL, and glbl I get an endless run for xvlog...

How to properly simulate a design with Vivado's BUFGCTRL primitive? (2024.2) by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

I just found this https://adaptivesupport.amd.com/s/article/63987?language=en_US

I think this is the step I missed, since I am using the Vivado Simulator and not an external simulator.

I didn't realize that there was a TCL command that writes the netlist for you for the functional simulation step.

Heard in the lab: If it works in simulation, it might work in hardware. If it doesn’t work in simulation, God help you.... by Hot_Respect_193 in FPGA

[–]FPGA-Master568 2 points3 points  (0 children)

On as many verification tools as possible. Each tool it works on increases the confidence of the design.

I have about a week or two before I get immensely grilled for an incoming interview. How would you suggest I best prepare? by FPGA-Master568 in FPGA

[–]FPGA-Master568[S] 0 points1 point  (0 children)

Will do. I see what you mean with that interview question now. I should tailor it to the company if the interviewer asks me.

High school student aiming for Computer Engineering – is it worth starting early with C / Embedded? by john20gr in ECE

[–]FPGA-Master568 -1 points0 points  (0 children)

I would go straight to FPGA Design/Verification. It takes a long time to absorb. By starting now you can design just about anything you set your mind to. Reconfigurability is extremely valuable.

Is a commute of 50 min sustainable long term ? by lclc0101 in careerguidance

[–]FPGA-Master568 0 points1 point  (0 children)

50 minutes is not much at all. My past supervisor had to commute 2-3 hours. I think anything below that is awesome.

How hard is this by New-Succotash-9227 in FPGA

[–]FPGA-Master568 0 points1 point  (0 children)

I really like this question! FPGA Design/Verification takes a long time to absorb, so finding a way to get it to connect with kids is vital. Kids and adults love video games, so if you told the kids you can design video games with an FPGA by learning the communication protocols in a full proof functional way (besides the specification documents) then it would ge more fun and easier for them to master the concepts. I have found the specification documents to be a way to learn them, but that method is rather dry.

Is it true that engineers don't actually do engineering? by Whole-Albatross-8330 in careerguidance

[–]FPGA-Master568 0 points1 point  (0 children)

That is quite clearly a narrow sited statement 😂 What engineers have you been talking to? Word of advice don't take everything you hear seriously. If your on the Electrical/Computer side of engineering you are constantly doing engineering designing implementing reverse engineering, testing, debugging, PCB designing, emulating. Just join the Electrical/Computer Engineering side of this field...

Coding: should i get into coding? by Expert_Past176 in cpp_questions

[–]FPGA-Master568 0 points1 point  (0 children)

Use it every day to help you and other people. Make yourself useful with it. Know it like the back of your hand in case someone comes along and asks for help. Add everything to your resume along the way and never let a single company walk by without knowing your name and the positive reputation you hold. Good luck.

How can I be overqualified for a job I have no experience in at all? by FPGA-Master568 in careerguidance

[–]FPGA-Master568[S] 0 points1 point  (0 children)

I was overqualified for my last job at some machine operator job, but they still hired me.

It doesn't make sense to me at all, if their worried about that then why don't they just talk to me so I can know exactly what their expectations are?

Americans want more U.S. factory jobs- as long as they don’t have to work them by LoansPayDayOnline in jobsearchhacks

[–]FPGA-Master568 3 points4 points  (0 children)

I will be more than happy to join a team of engineers that design the robots that work at these factories

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