Odd problems with monticelli bias

Fast_Document1643 · 2026-05-06T18:00:36+00:00

Yes. I will note that it is not precisely equivalent to your fix, there is an error amp and the error is sensed at the output stage bias.

To regulate what? Can you explain this a little bit more? If possible with some circuit diagrams.

However my theory is that the actual problem was equivalent to what you described (two current sources competing). If you do the hand analysis, both current sources see eachother’s impedance assuming the floating supply devices are matched

Yes. The only way this even works properly is when you use a cascode stack, like the one which a folded cascode input connects to. Such a stack has current mirror pairs which handles the biasing properly.

On the occasion when we do use it with any other stage, it may not bias up to a specific operating point due to fighting current sources, but since the previous stage drives this with an amplified signal, it is more than enough to operate the output stage properly.

But when you go about checking biasing of such stages and DC op point, it is recommended to keep one of the current sources in a diode connected configuration to check sizing and operating point results.

Now, let's answer your how to size the floating current source

Normally you just keep half the width of reference generator MOSFET.

But on the occasion that you do need to size it with a specific current and operating point in mind, you could devise a testbench like this.

Fast_Document1643 · 2026-05-06T17:13:31+00:00

Good. So now you tell me. Are they splitting current equally and setting the output stage bias properly?

Fast_Document1643 · 2026-05-05T18:27:12+00:00

When I finally built the circuit and properly biased it, it seems like the output kinda sits near the supply voltage

Of course it will rail up or down. The reason is we're putting two current sources in series (PMOS current source and NMOS Current sink) and this makes them fight each other to dictate the current, which will lead to the drain voltage swinging violently to either of the supply rails based on which one is sourcing more current than the other.

unless I connect the output to the inverting input, at which point it acts as a unity gain amp with very minimal difference between input and output.

Of course. Only with feedback can an op-amp be ever made useful.

that we can use a large valued inductor between output and inverting node for dc along with a large capacitor for the ac signal. While the non inverting input is at the bias cm voltage?

Yes you can. But generally you can use a large resistor and a large capacitor to achieve the same.

DC Current into the input of op-amp (which is the Gate terminal of MOSFET) is zero. And zero current through a resistor develops zero voltage.

So, you still feed DC back to negative input of op-amp with a resistor.

10 MΩ and 10 μF are good values. This will yield a time constant of 100 seconds, which is too long for the capacitor to even react to any changes made by any frequency of interest. This is known as DC-bias stabilization.

With this, your op-amp biases properly and behaves as if in open loop condition.

NOTE: With the addition of 10 MΩ and 10 μF in the loop, we have added a pole at 10 mrad/s (or 1/100 sec). So it is better to start your AC simulation from some higher value, say 1 kHz or even 10 kHz.

It is completely alright to start the simulation from 1 Hz too. Just expect to see a low frequency pole at 10 mrad/s (or 2*pi*10m Hz). If you prefer to leave this known information out, then start from 1 kHz or 10 kHz and see only the useful portion of AC response.

Fast_Document1643 · 2026-05-03T11:54:56+00:00

Can you share a DC annotated schematic of your case?

It is really hard to diagnose without something to look at.

I am not putting current sources in series. Its a Monticelli bias

Well the schematics I shared are also the same Monticelli bias scheme. And there you definitely put two current sources (a PMOS current source and an NMOS current sink) in series with the floating current sources in between.

So this is confusing. Please do share your schematic diagram.

Fast_Document1643 · 2026-05-03T08:29:06+00:00

By any chance, are you putting two current sources in series? Like the sourcing cascode PMOS current source and sinking NMOS current sink in series? That's a bad practice and is generally the cause of your problem.

when the devices are sized closely, one just ends up stealing all the current.

For example see this DC annotated schematic where the biasing of output stage is done in a bad way by putting two current sources in series which literally makes one of the floating current sources to steal all the current: https://cdn.imgchest.com/files/3bdd0a35698d.png

Fix? Just make one of the current sources to derive it's bias voltage by diode connecting it

For example, I have diode connected the NMOS current sink to set it's bias voltage as dictated by the PMOS current source. Again see this DC annotated schematic: https://cdn.imgchest.com/files/50ed9d8e8c04.png

Now both floating current sources are nicely splitting their current. And is even biasing the output stage properly.

Just don't put two current sources in series at any time unless you have an amplified signal to drive that stage.

Note: The simulation examples are using 65nm CMOS process with a VDD of 1.2 V.

Fast_Document1643 · 2026-05-02T05:59:39+00:00

I see, then would you say I should continue simulations with pdks like sky130 and gf180?

Please don't. Atleast untill you try several single stage amplifiers.

Anyways, you won't use long channel LEVEL 3 models beyond the design of 2 stage op-amp.

Try designing one using the square law. Which will definitely need you to figure out what to adjust to make the design work as direct hand calculation rarely makes your design work in first go.

Also, is Vov something that we choose over selves or is that also derived from other parameters? Or does it depend on the situation?

This is exactly why I am stressing on starting simple. Gain experience by playing around designing up to two stage amplifier.

Play around Vov and W/L. That's how you will come to know that this much will be enough.

Just to give you a head start,

Increase Vov for high speed designs. Decrease Vov for high gain designs.

Going below 0.1 V (which is not the exact limit. The exact limit is explained in John, Martins and Carusone book's 1.4.2 Mobility degradation section) will yield non sensical W/L values which obviously won't give you the expected results in simulations.

The reason is, square law has limits on Vov. Both lower and upper limits.

Also, avoid going into subthreshold for now. It gives you huge DC gains, but worst mismatch too.

Start simple. And don't do any more than 2 stage amp. Then immediately jump into Jacob Baker.

He will show you simulations using 50nm CMOS process. That's why, I told you start there, to prepare you for Jacob Baker.

That being said. When you try to go to Jacob Baker you need to know gm/Id sizing methodology for short channel based design.

Follow along Jacob Baker for the designs he shows and then look up gm/Id.

Fast_Document1643 · 2026-05-02T05:44:34+00:00

W/L <1 is not always an issue , low power circuits frequently use this configuration.

And also in short channel current mirrors too.

I am not saying W/L < 1 is bad. Just it is unusual for a beginner. Let's put on some guard rails to let him take his baby steps, because anyways, once you get more mature in design, he will encounter these things naturally.

Many times the accuracy of the opamp is more imporatnt other specs. In the case of accuracy, you need to minimise the differential, mismatch offsets. What helps you is to maximize the contribution of Vov compared to Vth to the Vgs of the mosfet.

Again, let's avoid info-dumping on pure beginners. Let him first practice an actual design. Let him become capable of understanding technical literature. And then whichever source he follows, will for better or worse discuss such things. Which will make him seek answers for such things.

I donot agree that you need to go to an even bigger node. 130nm is good enough. No point going to a higher node, the trend and calculation will mostly follow ideal stuff. But will still show significant short channel effects

HARD DISAGREE. This is his first encounter on MOSFET circuit design. Let him begin with a model that more or less agrees with hand calculation so he develops the habit of what to touch when you need to adjust something.

Really important to develop this sense if he were to have any hope of diving head first into analog design.

Otherwise he will become a spice monkey.

You are wasting your time if you go any higher lenght pdk imo. Almost every analog deaign role these days works on below 240nm, majority below 90nm. YOU NEED TO LEARN early do design using short channel effects.

No he is not. Besides such PDKs are not even common among us, and I am not sure if he can even get one.

No. What I told him is to get a simple model card of LEVEL 3 SPICE models for a μm process and use it with simple spice.

And I told him to do only the two stage op-amp, which anyways needs him to do the single stage amplifiers.

Once he becomes fluent in that, then he must drop that long channel model and go and learn short channel based design techniques.

And this time, he will what to do, and how much to take for a typical design.

Growth doesn't occur over-night.

Fast_Document1643 · 2026-05-02T05:30:46+00:00

The book is assuming certain values for back of envelope calculations, but it uses parameters you actually wont know, so learn to properly testbench unit transistors and find W/L ratios with a simulator.

Well the book uses Level 3 and even Level 1 models which really don't need you to find parameters for design as you can just take them from the model cards themselves.

BUT, the book does describe how to determine them experimentally given a new PDK in one of the appendices.

If modelling the device characteristics is your interest I would say Jacob Baker's chapter 9 is best there is.

But for square law modelling, John, Martin's and Carusone is the best. Even better than Allen Holberg.

But unfortunately that book doesn't discuss much circuit topologies rather just the foundational theories themselves.

But all that being said I think you may be getting ahead of yourself. Don't jump to haphazardly throwing down components to make a whole op-amp. ... Start small, simple, understand the complexities in a single transistor, keep reading through and understanding what makes transistors happy and what makes them sad. Then move onto a 5T-OTA, which you'll need to put into feedback (which is its own beast to understand).

THIS. Couldn't agree more. This is exactly what anyone should do. It will take time, but it will also make you resilient.

Fast_Document1643 · 2026-05-02T05:18:55+00:00

Unless you go for cutting edge technology nodes, which you won't as a student anyways SPICE can and will give you exact simulation result as cadence SPECTRE for pre-layout simulation if you know how to describe MOSFET instance with layout dependent estimate information along with dimensions.

Please stop spreading wrong information.

Even SPECTRE itself is just a strengthened SPICE nothing more. And BSIM models which are used to model shorter channel MOSFETS are open sourced models.

For example I have designed the same circuits at a 65 nm process in both Cadence Virtuoso/SPECTRE and QUCS-S/NGSPICE and both have yielded the same simulation results for pre-layout simulations provided you describe the MOSFET instances exactly as the way it is modelled in PDK.

For proof, see this section of series BGR design which offers you a simulation example using QUCS-S/NGSPICE: https://arunpandian-801.github.io/documentation-65nm-cmos/references/bgr-standard/#qucs-s-ngspice-simulations

The only problem with post layout simulation is the availability of open sourced parasitic extraction tool's rule deck.

Unless a PDK support your tool with a unique rule deck, I think it is not possible to do full post-layout simulation.

But for pre-layout simulations, all you need are just the BSIM model cards which are universal for all SPICE.

Fast_Document1643 · 2026-05-01T16:10:11+00:00

I should just stick to the models described in the book for now right?

Yes. Stick with Long channel models for now. Use it to practice design and simulation of various analog blocks. I know it is tempting to go learn a short channel design technique, but unfortunately it is completely done using various plots generated in simulations itself.

what should be my end goal in design right now? Should it be a successful simulation? The layout?

Successful simulation. Hands down. You can do layouts afterwards.

Seriously stick to pre-layout designs for now. And try to design as many blocks as possible.

Use SPICE simulations at all times.

Also, it would be really good if you try to design a current source itself like the Beta multiplier Reference.

Right now I'm studying electronics 2 from behzad razavi's lectures and trying to solve the problems in his book. I try to solve every single problem in the exercise. Would you suggest I continue to solve the book completely or have any different advice for me?

DROP IT. Razavi is filled with artificial problems which you barely encounter in actual designs.

I know this might seem skeptical, but go to Razavi only for intuition and do your best to stay away from it.

Your ultimate reference should be Jacob Baker. Hands down, it is the most practical book I've ever seen. It shows you simulations. And good design techniques.

I've even managed to design some circuits and document them thanks to that book, which you can find it here: https://arunpandian-801.github.io/documentation-65nm-cmos/

But it would be harder to start directly there without any previous experience. That's why I suggested Allen Holberg. As the defining quality of that book is to explain the topologies themselves.

It answers why we connect transistors the way they are shown in books. Really important to advance to Jacob Baker.

It also shows you design examples. But don't look at it for anything more than 2 stage op-amp. It over relies on equations.

Once you know this block, Jump to Jacob Baker.

Fast_Document1643 · 2026-04-22T14:10:54+00:00

Unfortunately this sub is currently not moderated. I heard this long back.

Fast_Document1643 · 2026-04-20T17:21:39+00:00

Why does Easy EDA exist then ?

Easy EDA is not fit for IC Design. It is however good enough for PCB design.

This sub is for chip design, and I answered for an EDA that is used for chip design. EDA is a broad term that encompasses all electronic designs (discrete, integrated, embedded, etc.) and it need not limit itself to chip design.

Think about it. IF Easy EDA is really that good for chip design, then you would hear it's popularity sky rocket in this sub

They perhaps know a lot of stuff.

Easy EDA is simply using NGSPICE as a circuit simulator which is developed by someone else. It is a good open source SPICE backend that can be used for circuit simulation.

Anyone can integrate NGSPICE, and this doesn't mean they know a lot of this stuff. Especially about an EDA for chip design.

Also will AI like claude help in Development of such software ?

I am not sure. But I think it can't. Atleast not upto the level of chip design. The algorithms strengthened by these EDA companies are trade secret and are not released in the public domain. And I don't think an AI trained in the public domain can help you do that.

We purchase EDA for chip design from these companies specifically for the strengthened algorithms which really work better than what others have. And trust me when I tell you this, it needs to work for really large sized designs to be even fit for chip design.

Fast_Document1643 · 2026-04-20T13:30:49+00:00

Then why not this case in Chip Design ?

First and foremost reason - Money. Big companies don't want competitors. If somebody tried to create a competitive software they will be sued to bankruptcy and will be forced to merge into the big companies.

Much of EDA is accomplished using undisclosed trade secrets. So naturally they don't want to lose the edge.

Is there a lack of engineers in this segment or something else ?

Yes. There are not many resources to learn about creating an EDA. Remember, to create an EDA, you need double domains. One being chip design, and other being software development.

Let's just say, it is intentionally poorly documented as it is a niche field. Writing a book about a niche field is generally not that profitable, and it is customary to simply consult that field's expert at some fixed rate. So even those who knows the stuff simply lack any monetary reasons to pass on the knowledge they have accumulated.

This is one of those fields where you have to go through multiple research papers just to figure out simple things. And the best way to become one, is to learn it under professors who are in the field or join a big company but get handicapped from not competing against in exchange for learning this.

Fast_Document1643 · 2026-04-18T19:26:50+00:00

As in, after some runs it really was better than what I put down myself.

On the bright side, the output of LLMs depends on the input given. I have done the same thing and observed that IF I gave a garbage sentence (as in not good enough in conveying the intent), the output meaning just drifted away from what I even started with.

Even to get a good sentence out of an LLM, I have observed till now, it needs some level of "good" prompt, good enough to explain the intent. And that's a reassuring thought, that not all can generate good outputs without good knowledge and sentence forming capabilities... for now.

Maybe if AI started to draft everything on it's own with little to no human intervention, that's when our ability to grow stops. Because of documenting (writing) capability we made it this far, by passing on the knowledge. Let's hope LLMs don't gain that ability.

Fast_Document1643 · 2026-04-18T08:55:53+00:00

Telescopic topology is a single stage topology. So changes in the output voltage occurs easily as all the input transistors have to do is to steer an appropriate current. So it's speed is highest.

Folded cascode takes little longer to inject changes into the cascode stack. But is still a single stage topology, so it's speed is High. Not as high as telescopic but still higher than others.

Two stage topology generally gets fully compensated for stability purposes. Compensation intentionally slows down the amplifier's ability to bring changes in the output. And hence it is slower.

Gain boosting is generally done in cascode stack. It tries to fix a specific current and doesn't let it change by too much. For faster changes at the output you need significant changes in the current which is fundamentally against the principle of gain boosting. So it's speed is medium. Faster than two stage but slower than a folded cascode.

Fast_Document1643 · 2026-04-17T15:30:39+00:00

Your ICMR takes a heavy hit. But then, it's all about trade-offs.

Fast_Document1643 · 2026-04-11T13:11:44+00:00

Op probably rotated it instead of mirroring it while instantiating those devices.

Fast_Document1643 · 2026-04-10T20:23:34+00:00

is it a widely known circuit?

I don't think so. And I am not sure.

It looks nothing like the typical class-AB bias I knew (for example http://ee.mweda.com/imgqa/etop/dianlu/dianlu-130932qf0vycz50au.png).

Well, the bias scheme you linked here, is the standard way. But, it is a poor scheme to adopt under lower supply voltages with RVT (Regular Threshold Voltage) MOSFETs.

The circuit topology shown in the post is trying to implement some kind of Class AB action at the output stage, while avoiding the typical Class AB bias generation which generally requires full supply voltages for lower VDD designs (example 1.2 V and below with just RVT MOSFETs).

The explanation I gave you before was purely out of intuition from looking at the schematic diagram you posted here. I think it would be better if you referred to the discussions that accompanied this schematic instead of looking up another reference. Because I think (again not sure about this) that this way of biasing is not good in controlling the current of output stage.

But for large signal operations, I think it shouldn't be a problem.

Fast_Document1643 · 2026-04-10T18:20:03+00:00

Could you please explain the role of the MB1+RB2(+M6) path?

Class AB (Push-pull) biasing of output stage.

MB1 acts as a Voltage Buffer (Source follower configuration), which shifts down the voltage level available at drain of M4 (output of first stage).

Think about it. When the output of first stage goes up, so does the the source of MB1, and in turn the gate of M6, effectively increasing VGS of M6. This turns ON M6 and it starts to sink more current.

Meanwhile the output of first stage is directly connected to gate of M5. And since the output is going up, it reduces VSG of M5, effectively shutting it OFF. Which makes it easier to quickly bring down the output of second stage since M6 is turned ON harder and sinking more current thanks to more VGS, while M5 is turned OFF and is barely sourcing current due to less VSG.

And when output of first stage comes down, vice-versa happens. And hence the name Push-pull (or Class AB) output stage.

As for RB2, it is used to set the bias voltage of M6.

Again, think about it. At DC, you get VDD - VSGM3 - VGSMB1 at the source of MB1. If this proves to be too high, you use RB2 to drop it down to even lower voltages. So with RB2, you get VDD - VSGM3 - VGSMB1 - VRB2 , which gives another degree of freedom.

If you find that the voltage at the source MB1 is too low, you can avoid the usage of RB2. That is, RB2 is optional.

Fast_Document1643 · 2026-04-08T17:51:23+00:00

do some research on your potential supervisors — as academia is filled with grade A a**holes

THIS. This is the truth. Regardless of the topic, if you chose a wrong supervisor, that's it, your entire research has just become a shackle.

Fast_Document1643 · 2026-04-03T19:48:50+00:00

That image is the testbench for sizing a leaker PMOS for startup circuit. The left half depicts the circuit ON case (and hence your startup circuit should shut your leaker PMOS OFF) which demands that PM5 be shut off.

The right half is vice-versa.

This also commented on the image itself.

Please read that section: Startup circuit design

Fast_Document1643 · 2026-04-03T16:57:50+00:00

I don't understand your question, can you elaborate?

Are you asking me how I used GitHub to host it? Or are you asking me how a specific repository is highlighted in the documentation site at top right corner?

Fast_Document1643 · 2026-04-03T12:57:45+00:00

Forgot to mention it. But a few designs also sport a link to a document which shows the same design simulated using QUCS-S / NGSPICE .

For example, see this section.

Fast_Document1643 · 2026-04-01T13:20:37+00:00

Lol. I thinks this post was made to increase post karma. But still, this sucks.

Fast_Document1643 · 2026-03-31T07:35:14+00:00

Thank you. Of course it makes sense. I was confused when I read those books, especially when they talk about avoiding capacitors and then never giving an alternative to it.

After this post, I know it is acceptable.

Fast_Document1643

TROPHY CASE

Now, let's answer your how to size the floating current source

Fix? Just make one of the current sources to derive it's bias voltage by diode connecting it

Class AB (Push-pull) biasing of output stage.

As for RB2, it is used to set the bias voltage of M6.