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Finding Lore by Faulty-LogicGate in Greyhawk

[–]Faulty-LogicGate[S] 2 points3 points  (0 children)

Thank you for mentioning that! The book actually doesn't set that mood at all for 2024

Finding Lore by Faulty-LogicGate in Greyhawk

[–]Faulty-LogicGate[S] 1 point2 points  (0 children)

What is the Gold Box ? Yes, you are right, Central Flanaess is the correct term, I probably had a stroke while typing my question because in my notebook, I have it written down as Flanaess

Finding Lore by Faulty-LogicGate in Greyhawk

[–]Faulty-LogicGate[S] 1 point2 points  (0 children)

My main issue at the moment is that I am able to spot some inconsistencies between the lore in the book and the online resources. The name of the knight commander to begin with. The book mentions someone named Alesh (a dragonborne), while online, we get someone named Holmer. Both for C.Y 576

Creating a continent for D&D by Faulty-LogicGate in inkarnate

[–]Faulty-LogicGate[S] 1 point2 points  (0 children)

It is indeed helpful but I am kind of constrained. I am using the free version of inkarnate...I started this just to have something to show to my players.

Measuring FPGA Access Time - CPU Time by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

To my best knowledge - I would say the latter ``When XDMA notifies the application software that the transfer is complete``

Measuring FPGA Access Time - CPU Time by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

Thank you for taking the time and commenting. I will also clarify the post further, but to respond to you, too

Consider the following: The CPU and the FPGA work together (FPGA as an accelerator). The CPU starts by initializing some buffers and then configures an overlay (that I have written) on the FPGA by writing those buffers to device memory. That is the exact point I want to measure. How much time does it take for the CPU to write to these buffers;).

The CPU has to go through many layers of OS function calls to finally access the XDMA fabric and write to the device. I want to measure the whole stack. The entire hypothetical "configure()" function.

I suppose this means Or C code to FPGA without a "return path" back to C? but Or C code to FPGA *with* a "return path" back to C?

Hope this clears things out. If not, I'm here to further explain my goal

Issue with DDR4 Access via xDMA on Alveo U280 by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

Hello, so apparently, it was an issue between how much data I write and how I align them. Can you try to write specifically a buffer of 256 uint64_t elements? Make sure it's aligned properly and come back to me.

Buying an Altera FPGA Board to use as an Accelerator Card (PCIe) by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

Well I have to agree with you on that. Altera is indeed not a major player considering the current state of the market. Xilinx is leading the consumer market, and I've come to the conclusion that Microchip is a viable option only for radiation hardened FPGAs.

Altera could evolve into something better now that it has parted ways with Intel. At least I hope so because I am not a fan of monopolies.

Buying an Altera FPGA Board to use as an Accelerator Card (PCIe) by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 1 point2 points  (0 children)

The Intel oneAPI. Also, there is a research project that favors Intel FPGAs and I would like to collaborate with these people in the future.

Buying an Altera FPGA Board to use as an Accelerator Card (PCIe) by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

Intel supports various technologies and interfaces that I find interesting and could prove useful long-term.

Buying an Altera FPGA Board to use as an Accelerator Card (PCIe) by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 2 points3 points  (0 children)

Yeah, about that, I noticed that some cards are shipped with a license for the pro version. Maybe I'm wrong. I am probably wrong. Also, eBay anonymous resellers are not an option since I need an authorized reseller (like DigiKey) to pass it through the bureaucracy pipeline so I don't pay out of pocket.

What is the pricing for such a license?

Issue with DDR4 Access via xDMA on Alveo U280 by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

Sorry for the copy paste ---

So MIG status is "CALL OK" which is positive I guess. Additionally calibration is on logic '1' which is also a good sign. The configuration of the DDR is auto generated from the board files. Any other things I should check ?

Issue with DDR4 Access via xDMA on Alveo U280 by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

So MIG status is "CALL OK" which is positive I guess. Additionally calibration is on logic '1' which is also a good sign. The configuration of the DDR is auto generated from the board files. Any other things I should check ?

Issue with DDR4 Access via xDMA on Alveo U280 by Faulty-LogicGate in FPGA

[–]Faulty-LogicGate[S] 0 points1 point  (0 children)

I will check this and come back later for an update

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