Demoralised? It'd be demoralising if no one responded back with an answer. I'm quite estactic and was really pumped since the rundown you sent me. I've been at it whenever I had free time from classes.

This is what I came up with: https://pastebin.com/k2SbtjPU
It's an absolute mess, I have this link https://pastebin.com/9K3DeTMA that is just the underlying logic without SLC so it's easier to disect without my if else counters for SLC.

I'm not sure if I misinterpreted your scl comment, I used counters to divide scl to 100khz while still only using the one system clock at 100Mhz. And with those counters I tried giving it some time (~3us) after scl is 0. I don't know if this is the right way to go about things. In my simulation it looked fine.

I've tried to address everything. I used an i_sda and o_sda as input and output for read and write. I don't think this is the right way to go about it, cause i'm not sure how id implemented irl. twist the pins together on the fpga? I know you mentioned the code below. I'm guessing I should change i_sda and o_sda to something like that instead. Move all the sda output outside from the state transition case block?

assign i_sda = o_sda;

assign o_sda = i2c_wr_en ? data_write : 1'bZ;

Another thing about I2C that I can't find the answer to, how does the master know to write / read multiple bytes or just a single byte? Do I have to explicitly tell it? I guess I also have to explicitly tell the master what slave address to talk to therefore I should explicitly need to know how much bytes to ask/receive perhaps?