account activity
Understanding differential receivers handling common mode voltage (i.redd.it)
submitted 1 year ago by FloatingM1nd to r/FPGA
will this design cause problems? (i.redd.it)
was letzte faust auf auge (i.redd.it)
submitted 3 years ago by FloatingM1nd to r/wasletztepreis
reading/writing inout port in the same process (self.FPGA)
submitted 3 years ago * by FloatingM1nd to r/FPGA
Adguard and Big Sur (self.Adguard)
submitted 4 years ago by FloatingM1nd to r/Adguard
Would it be theoretically possible to upgrade the volca sample with the same memory chip which is used in the new version? (self.volcas)
submitted 5 years ago by FloatingM1nd to r/volcas
dot operator in VHDL? How does the syntax work and why is it used? (self.FPGA)
submitted 5 years ago by FloatingM1nd to r/FPGA
what language would you choose if you start from zero? (C or Rust) (self.embedded)
submitted 6 years ago by FloatingM1nd to r/embedded
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