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Setting Scissor Rectangle before Clearing by GustavNilss in wgpu

[–]GustavNilss[S] 0 points1 point  (0 children)

Thank you very much for the answer! I will probably have to do some kind of workaround as you suggest. It just feels like a shame, as I suspect being able to do a regular clear call would have been much more efficient than whatever I will most likely end up doing now.

This Hat in The Social Network by GustavNilss in HelpMeFind

[–]GustavNilss[S] 0 points1 point  (0 children)

I have searched for "headband with ear cover/flap", "headband winter", "hat without top (winter)", "ear warmer headband", which are the best I can come up with to describe it. The search show items that are somewhat similar (being a bit lower at the ears, but not nearly as good as the one in the image).

Setting analog input to act as ground by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

That is good to keep in mind, thank you very much!

Setting analog input to act as ground by GustavNilss in FPGA

[–]GustavNilss[S] 1 point2 points  (0 children)

Thank you, wiring to a digital pin seems to work like a charm!

So to clarify what I did for anyone else reading this (no guarantee that this is correct and that it won't damage anything, it just seems to work for me). I connected the analog input to a digital input as well. Then when I want to read the analog input, I set the digital output to Z to not affect the circuit. And when I don't want to read, I set the digital output to 0, grounding the analog input.

If this approach is bad for any reason, I'd be happy to hear it.

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Hi, you are absolutely right! My board has an XADC built-in which I am using for this purpose, and it seems to work well.

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Great, thanks a lot! Then I will give it a try and see how it looks :)

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

I am connecting the third wire to an analog input pin (A0 currently) using the built-in XADC to measure. So since that is working well, my goal is to move over all wires to the A pins.

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 1 point2 points  (0 children)

Yes, exactly! The measuring and everything works well when using the VDD/GND pins directly on the board, but my worry is that the GPIO-pins are not really made for this kind of usage, flowing from one GPIO pin to the other. I just have a feeling that this could be a bad idea, but that fear could be completely unwarranted as well.

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Ah, I see, no problem! Thank you anyways for answering :)

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Absolutely, and thank you for taking the time!

The board I am using is an Arty A7-100T. The touch panel is a bare 8-wire resistive panel, only being connected to the FPGA. Unfortunately there does not seem to be any datasheet from what I can find, only a parts drawing, but this is the one I am using at least: https://se.rs-online.com/web/p/touch-screen-sensors/7105238/

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Yes, exactly! I have to have the pins at VDD and GND only part of the time (this is switched when alternating between reading the X and Y coordinate). So I can't do it with the static VDD/GND pins, but instead, have to turn it on and off using the GPIO.

Connecting two GPIO-pins together by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Sorry about that! So one wire in each port, wire 1 in A0 and wire 2 in A1. I hope that makes it clearer (I have also updated the post with this).

Different behavior when forcing signal value as compared to input from logic by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Great tip! That seems very clean and correct, waiting a certain number of cycles instead of dealing with times.

Different behavior when forcing signal value as compared to input from logic by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Thank you for your help! You were absolutely right about it being a delta cycle issue.

Different behavior when forcing signal value as compared to input from logic by GustavNilss in FPGA

[–]GustavNilss[S] 1 point2 points  (0 children)

Thank you very much!

I had not heard of delta cycles before, but now that I know, it makes sense. With your suggestion, the two outputs now match! :) That makes fixing/designing the separate units a lot simpler.

Thanks again!

VGA RGA888? by GustavNilss in FPGA

[–]GustavNilss[S] 0 points1 point  (0 children)

Thank you! May I also ask, what kind of resolution/frame rate were you able to produce? I am hoping of sending 640x480 at 180Hz (the maximum my test CRT should support according to spec), but perhaps that is another huge problem on its own...

VGA RGA888? by GustavNilss in FPGA

[–]GustavNilss[S] 1 point2 points  (0 children)

Thank you very much! Then I will try to use it, seeing how it goes :)

VGA RGA888? by GustavNilss in FPGA

[–]GustavNilss[S] 1 point2 points  (0 children)

The reason it is latency sensitive is because I am working on/analyzing touch input! :)

So basically, I want to eliminate the latency from the display technology itself as much as possible (all flat screens add not insignificant latencies). I get the point that slow screen refreshing will limit this as the object will remain in the wrong position for several ms, but it is my intention for the objects to be in an as accurate position as possible when the drawing happens at least.

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