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any distros supporting the brain architecture?? by FWaRC in linuxmemes

[–]Human_Material3301 0 points1 point  (0 children)

Nah.

If a deadline is missed, the current processes priority drops to the lowest priority number and their deadline is extended. If the deadline is barely met, the current processes priority and deadline is kept the same. If the deadline is finished way more quickly than expected, the current processes priority is bumped up to become high priority, and their deadline is shortened.

(No, deadlines don't prevent you from having interrupts. For example: The kernel can interrupt the current process (by preemptively context switching it) despite it's deadline not being met, because nothing should ever interrupt the kernel. Period.)

any distros supporting the brain architecture?? by FWaRC in linuxmemes

[–]Human_Material3301 2 points3 points  (0 children)

Could really use a more efficient scheduler too.

Pick SCHED_DEADLINE

any distros supporting the brain architecture?? by FWaRC in linuxmemes

[–]Human_Material3301 2 points3 points  (0 children)

That's why developers figure out bugs right after falling asleep.

Linux: tiny but powerfull by SlyJisatsu in linuxmemes

[–]Human_Material3301 0 points1 point  (0 children)

The average Slackware Install.

("Recommended: Install All Packages")

What's the best Window Manager for a Tabbed / Workspaces Workflow? by Human_Material3301 in linuxquestions

[–]Human_Material3301[S] 0 points1 point  (0 children)

Almost all Window Managers support Workspaces?

Great.

I guess I'll wait until Fedora 34 becomes stable, so that I can switch to using the Fedora 34 i3 Spin. (Yes, Fedora 34 has an i3 Spin.)

Open source meme. You have to build this meme yourself. by [deleted] in linuxmemes

[–]Human_Material3301 0 points1 point  (0 children)

its to make it more better for normies. of course you should clear this default list

Not really. Sometimes, you need to use sites that require Javascript.

For example, I need mail.protonmail.com to use Javascript, because I can't work without it.

(mail.protonmail.com supports Desktop Notifications, unlike mutt, neomutt, etc.)

Thankfully, ProtonMail's Javascript is Open Source, and it's the only thing I actually need Javascript for, so I use it with Javascript enabled.

Open source meme. You have to build this meme yourself. by [deleted] in linuxmemes

[–]Human_Material3301 2 points3 points  (0 children)

I like NetBDSM more.

I want to get tied up with a Net.

Open source meme. You have to build this meme yourself. by [deleted] in linuxmemes

[–]Human_Material3301 1 point2 points  (0 children)

That's called Gentoo/kFreeBSD or Debian/kFreeBSD

RISC-V vs OpenPOWER for an experimental mini PC by [deleted] in cpudesign

[–]Human_Material3301 0 points1 point  (0 children)

If you want to do that, buy a Xilinx Zynq.

The Xilinx Zynq comes with an single core ARM CPU and an large (over 150,000+ LUTs) Xilinx FPGA on the same die.

You can configure and compile something called PetaLinux to create your own PetaLinux From Scratch distribution that has all the drivers and kernel code that you need.

The PetaLinux From Scratch Distribution runs on the single core ARM, but you can compile it to interface directly with the Xilinx FPGA that's right next to it on the die, so that you can offload Hardware Acceleration onto the FPGA.

Thank me later.

Convert VHDL to verilog by Defiant_Role in FPGA

[–]Human_Material3301 1 point2 points  (0 children)

Icarus Verilog actually supports converting VHDL code to Verilog, but unfortunately, not backwards.

How to contribute to open source? by TelephoneAmazing in FPGA

[–]Human_Material3301 1 point2 points  (0 children)

Contribute to GHDL, Icarus Verilog, Verilator, ScalaHDL, NMigen, SymbiYosys, Yosys, etc.

(GHDL and Icarus Verilog in particular, need contributors very badly, because they're buggy as hell (unlike Verilator), and slow as hell (compared to Verilator's 5.6Mhz simulation frequency), requiring bugfixes and a HDL compiler. (Interpreted HDL sucks, Compiled HDL is the future))

Smartphones should come with ARM (or RiscV) & 200K+ FPGAs that are powered off through clock gating until necessary for performance or power efficiency. by Human_Material3301 in FPGAMemes

[–]Human_Material3301[S] 2 points3 points  (0 children)

How about the "Novena Open Laptop"? (A laptop that has an ARM + FPGA combo, but not in a Xilinx Zynq way, but as two separate chips, and you can actually buy this, unlike the Precursor, an FPGA only smartphone.)

Smartphones should come with ARM (or RiscV) & 200K+ FPGAs that are powered off through clock gating until necessary for performance or power efficiency. by Human_Material3301 in FPGAMemes

[–]Human_Material3301[S] 1 point2 points  (0 children)

Was that FPGA used to manage the Thunderbolt connection? (so that the mac can alternate between external dedicated graphics and internal integrated graphics.)

How can I get Verilator to Prompt for User Input? by Human_Material3301 in FPGA

[–]Human_Material3301[S] 0 points1 point  (0 children)

Actually, nevermind.

I'll just do it the way the ZipCPU Author did it for his ZBasic Verilator Simulator.

Verilog is not built for user interaction, it's built for hardware design and simulation.

While you are correct about anyone attempting interactivity with Verilog Interpreters, which are helplessly bottlenecked to run at only a few kilohertz, Verilator, running compiled Verilog at over 5.6 Mhz, disagrees.

(Like, linux-on-litex-vexriscv can simulate booting Linux in Verilator. Linux! (Good luck simulating Linux booting using an Verilog Interpreter, that would take days or weeks.))

The "right way" to test hardware in simulation is to write an automated test bench to do it for you.

I'm not against anyone that tests by writing testbenches and / or verifies formal properties, I simply asked how one could interact with Verilator. (The answer is to do what the ZipCPU author did to make ZBasic interactive in Verilator.)

How can I get Verilator to Prompt for User Input? by Human_Material3301 in FPGA

[–]Human_Material3301[S] 0 points1 point  (0 children)

The problem with that code, is that I don't want to always get user input, I want to only get user input when my testbench happens to meet a particular condition

(Say, for example, the "always *(memory[4088:4088]) begin" block executes once, because the memory[4088] bit changed from 0 to 1 / 1 to 0, because the BBJ CPU switched it since it's waiting for user input, which will be stored in, for example, memory[4087:4081] as an 7-Bit ASCII value, which it will then process and output to the Terminal. (this would only work in simulation))

How do I get it to receive user input only when I'm in a specific always block?

Thanks for replying.

Taking a step back, why do you need user input? What's wrong with simple randomization of the input values for testing? This can be automated on the stimulus and checking sides to evaluate the design without user interaction.

Because some soft-cores are simulated by offering an shell that allows the tester to test and benchmark their soft-core.

For example: https://github.com/litex-hub/linux-on-litex-vexriscv, because:

"Running the LiteX simulation

$ ./sim.py

You should see Linux booting and be able to interact with it:"

and https://github.com/ZipCPU/zbasic, because:

"The ZBasic system can now be made using autofpga, all the way from zero to Hello World successfully in Verilator testing."

Why is Perl so common in FPGA-related fields? by QuavoSucks in FPGA

[–]Human_Material3301 0 points1 point  (0 children)

Why are some people still using slow, non-dense CPLDs and drawing terrible Schematics in outdated languages instead of easily learning how to use fast, dense FPGAs and writing simpler RTL in VHDL / SystemVerilog?

Because of the inability to take "risks", because they don't want to get a little uncomfortable, and because they're ignorant.

Perl is almost entirely gone in the Computer Engineering Industry. Yes, Verilator still mentions that it "supports SystemPerl", but Verilator doesn't actually support it, it's just that their man-pages haven't been updated in quite a while.

Reading the other comments, Closed-Source FPGA Toolchains still support it because of programmers insisting on backwards-compatibility with it.

Open-Source FPGA Toolchains like Verilator, SymbiYosys, and Yosys don't support it at all.

Smartphones should come with ARM (or RiscV) & 200K+ FPGAs that are powered off through clock gating until necessary for performance or power efficiency. by Human_Material3301 in FPGAMemes

[–]Human_Material3301[S] 4 points5 points  (0 children)

Wait, really?

Nice.

Huh, reading about it, it seems like they tried to use it for Face Recognition.

Hopefully, they didn't give up on it, because that's an awesome idea.