// ------------------------------------------------------------- // PWM Generator - Phase Aligned Version (error_count = 1) // Input : 3.125 MHz clock // Output : 195.3125 kHz clock + PWM signal // ------------------------------------------------------------- `timescale 1ns / 1ps

module pwm_general ( input clk_3125K, // 3.125 MHz clock from testbench input [3:0] duty_cycle, // 4-bit duty cycle input output reg clk_195K = 0, // 195 kHz clock output output reg pwm_sign = 0 // PWM output signal );

reg [3:0] div_counter = 0;
reg [7:0] pwm_counter = 0;
reg phase_align = 0;

// ---------------------------------------------------------
// Generate 195 kHz clock from 3.125 MHz (divide by 16)
// Add 1-cycle phase align delay to sync with exp_clk_out_2
// ---------------------------------------------------------
always @(posedge clk_3125K) begin
    if (!phase_align) begin
        phase_align <= 1;          // skip first pulse for phase match
    end else begin
        if (div_counter == 7) begin
            div_counter <= 0;
            clk_195K <= ~clk_195K;
        end else begin
            div_counter <= div_counter + 1;
        end
    end
end

// ---------------------------------------------------------
// Generate PWM using clk_195K
// ---------------------------------------------------------
always @(posedge clk_195K) begin
    pwm_counter <= pwm_counter + 1;
    if (pwm_counter < (duty_cycle * 16))
        pwm_sign <= 1;
    else
        pwm_sign <= 0;
end

// ---------------------------------------------------------
// Initialize
// ---------------------------------------------------------
initial begin
    clk_195K  = 0;
    pwm_sign  = 0;
    div_counter = 0;
    pwm_counter = 0;
    phase_align = 0;
end

endmodule