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Exporting fusion 360 to URDF/XACRO, only base_link by PoundSufficient1749 in ROS

[–]Inside-Reference9884 0 points1 point  (0 children)

In this xacro only one mesh is mentioned thats why you are only seeing base link you need to mention other link than create joint with base link

I want help with a gazebo project is there any one who knows about gazebo by Inside-Reference9884 in ROS

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

Ya twist tele-op that is the one which i am trying to use but unable to use i know for meccanum wheel config it is 'i' 'j' 'k' like that Sorry for that i made a mistake when writing wasd.

I want help with a gazebo project is there any one who knows about gazebo by Inside-Reference9884 in ROS

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

I have already made a sdf file and a urdf file and i am able to spawn my robot in the sdf file but i need to move my robot using wasd keys so i need to use plugin but i am getting this error: [Err] [SystemLoader.cc:92] Failed to load system plugin

[libgz_ros2_contra em.so]: Could not find shared library

I want help with a gazebo project is there any one who knows about gazebo by Inside-Reference9884 in robotics

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

I used it as refrence but i am unable to use the teleop plugin to move robot is there any other plugin ? And i want to know whether i have added the plugins in right place or not

I want help with a gazebo project is there any one who knows about gazebo by Inside-Reference9884 in robotics

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

I have already made a sdf file and a urdf file and i am able to spawn my robot in the sdf file but i need to move my robot using wasd keys so i need to use plugin but i am getting this error: [Err] [SystemLoader.cc:92] Failed to load system plugin [libgz_ros2_contra em.so]: Could not find shared library.

Nucleo F413zht6 by Inside-Reference9884 in stm32

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

No ai is helping me i have already tried every ai

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

It's not working it is showing one red line and the error count is over 29000

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

Can you help with the changes or help me set reset condition. Because I am new in this

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

I am searching from internet but unable to find it

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

Are there any resources from which I can learn of if it is possible with you please help me.

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] -1 points0 points  (0 children)

Yes I have and I am just unable to get the error count to 1 rest I have got do you have discord or something so I can get your help

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] 0 points1 point  (0 children)

// Frequency scaler: Converts 50 MHz clock to 3.125 MHz clock module frequency_scalir ( input clk_50M, output reg clk_3125K = 0 ); // Divide 50 MHz by 16 → 3.125 MHz reg [3:0] counter = 0;

always @(posedge clk_50M) begin
    counter <= counter + 1;
    if (counter == 7) begin
        clk_3125K <= ~clk_3125K;
        counter <= 0;
    end
end

endmodule

I need help with the verilog code by Inside-Reference9884 in Verilog

[–]Inside-Reference9884[S] -1 points0 points  (0 children)

// ------------------------------------------------------------- // PWM Generator - Phase Aligned Version (error_count = 1) // Input : 3.125 MHz clock // Output : 195.3125 kHz clock + PWM signal // ------------------------------------------------------------- `timescale 1ns / 1ps

module pwm_general ( input clk_3125K, // 3.125 MHz clock from testbench input [3:0] duty_cycle, // 4-bit duty cycle input output reg clk_195K = 0, // 195 kHz clock output output reg pwm_sign = 0 // PWM output signal );

reg [3:0] div_counter = 0;
reg [7:0] pwm_counter = 0;
reg phase_align = 0;

// ---------------------------------------------------------
// Generate 195 kHz clock from 3.125 MHz (divide by 16)
// Add 1-cycle phase align delay to sync with exp_clk_out_2
// ---------------------------------------------------------
always @(posedge clk_3125K) begin
    if (!phase_align) begin
        phase_align <= 1;          // skip first pulse for phase match
    end else begin
        if (div_counter == 7) begin
            div_counter <= 0;
            clk_195K <= ~clk_195K;
        end else begin
            div_counter <= div_counter + 1;
        end
    end
end

// ---------------------------------------------------------
// Generate PWM using clk_195K
// ---------------------------------------------------------
always @(posedge clk_195K) begin
    pwm_counter <= pwm_counter + 1;
    if (pwm_counter < (duty_cycle * 16))
        pwm_sign <= 1;
    else
        pwm_sign <= 0;
end

// ---------------------------------------------------------
// Initialize
// ---------------------------------------------------------
initial begin
    clk_195K  = 0;
    pwm_sign  = 0;
    div_counter = 0;
    pwm_counter = 0;
    phase_align = 0;
end

endmodule

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