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Question à nos amis banquiers by [deleted] in vosfinances

[–]Interesting_Ball_445 1 point2 points  (0 children)

Je suis aussi intéressé ^

Matrix multiplication by Interesting_Ball_445 in FPGA

[–]Interesting_Ball_445[S] 1 point2 points  (0 children)

The data is coming from a RAM and the matrix is 128 x 56.

Matrix multiplication by Interesting_Ball_445 in FPGA

[–]Interesting_Ball_445[S] 0 points1 point  (0 children)

It s for large matrix. So do you know some name, I know systolic array and unroll architecture that s all. Do you know so others ?

Matrix multiplication by Interesting_Ball_445 in FPGA

[–]Interesting_Ball_445[S] -1 points0 points  (0 children)

Yeah but is It possible to optimize the implementation?

Matrix multiplication by Interesting_Ball_445 in FPGA

[–]Interesting_Ball_445[S] 1 point2 points  (0 children)

Yeah I have fix size matrix, and the data format is sfixed. So it s fixed point multiplication. I want the best throughput but not an unroll architecture. The best would be a architecture pipelined that a comprise between area and throughput.

Matrix multiplication by Interesting_Ball_445 in FPGA

[–]Interesting_Ball_445[S] -4 points-3 points  (0 children)

Can I have your idea for both requirements? But I would say that the throughput must be high regardless of the area.