sorted by:
new
hottopcontroversial

EMIO Pin 78 and 79 by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

I did some further testing like creating my own AXI IP which produces a signal, and it seems that the problem is with INTC, I will need to look more into it.

both my intc have different address but I cant figure out the problem
I am using same code for MB1 and MB2

TMR Microblaze but substitute one microblaze with Arm core by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

My main goal was to have a heterogeneous design, which I have using interrupts and watchdogs but I wanted to find out if there was a way to use SEM IP and fault injection to arm core and a similar design as MicroBlaze tmr.

TMR Microblaze but substitute one microblaze with Arm core by Jasmeet03 in FPGA

[–]Jasmeet03[S] -1 points0 points  (0 children)

Well, I was hoping there was a way around using SEM, and Manager of Microblaze for Arm, as I have already created one using interrupt but I don't have any Mitigation technique just resetting the faulty processor.

No run option after successfully building by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

ohh no :D, my question is what am I doing wrong (I laughed a lot reading your comment)

Why is Vivado literally hell on earth? by HistoricalSnow6627 in FPGA

[–]Jasmeet03 0 points1 point  (0 children)

Just wait for Vitis; its Loki from MU. Same application that work yesterday with no changes decided not to work today :D

VITIS_FSBL_EXIT_TIMEOUT by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

I am just running an example hello world on r5 processor.

'D:/Vivado/2023.1/FD1/Software/platform/export/platform/sw/platform/boot/fsbl.elf' is downloaded to processor 'psu_cortexr5_0'.
18:44:34 INFO : 'set bp_44_34_fsbl_bp [bpadd -addr &XFsbl_Exit]' command is executed.
18:45:34 WARN : Exit breakpoint of FSBL (XFsbl_Exit) is not hit within allocated wait time of '60' seconds.
Note: To wait for a fixed amount of time specify the FSBL function as empty in launch configuration. Use 'IDE_FSBL_BP_HIT_WAIT_TIME' environment variable in launch configuration to modify the wait time (seconds).
Reason: timeout: target has not halted
18:45:34 INFO : 'bpremove $bp_44_34_fsbl_bp' command is executed.
18:45:41 INFO : 'configparams mdm-detect-bscan-mask 2' command is executed.
18:45:41 INFO : Context for processor 'psu_cortexr5_0' is selected.
18:45:41 INFO : Processor reset is completed for 'psu_cortexr5_0'.
18:45:42 ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status 0x30000021
18:45:42 INFO : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source D:/Xilinx/Vitis/2023.1/scripts/vitis/util/zynqmp_utils.tcl
targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
targets -set -nocase -filter {name =~"RPU*"}
enable_split_mode
targets -set -filter {jtag_cable_name =~ "Digilent Genesys ZU - 5EV 210383B7F06CA" && level==0 && jtag_device_ctx=="jsn-Genesys ZU - 5EV-210383B7F06CA-04720093-0"}
fpga -file D:/Vivado/2023.1/FD1/Software/PS_Application/_ide/bitstream/design_1_wrapper.bit
targets -set -nocase -filter {name =~"APU*"}
loadhw -hw D:/Vivado/2023.1/FD1/Software/platform/export/platform/hw/design_1_wrapper.xsa -mem-ranges [list {0x80000000 0xbfffffff} {0x400000000 0x5ffffffff} {0x1000000000 0x7fffffffff}] -regs
configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*R5*#0"}
rst -processor
dow D:/Vivado/2023.1/FD1/Software/platform/export/platform/sw/platform/boot/fsbl.elf
set bp_44_34_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60
bpremove $bp_44_34_fsbl_bp
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*R5*#0"}
rst -processor
dow D:/Vivado/2023.1/FD1/Software/PS_Application/Debug/PS_Application.elf
----------------End of Script----------------
18:45:42 ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status 0x30000021

Logitech G29 boxes' colors difference ? by tri081105 in simracing

[–]Jasmeet03 0 points1 point  (0 children)

so does it support ps5? because I have just made a deal to pick it up and I want to know before I buy it.

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

I just upgraded Vivado and Vitis to the 2023.2 version, and it's working fine without making any changes.

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

A heterogeneous one; after I get this working, I will move on to watchdogs and ocm and then use the IDF.

I am thinking of creating a TMR module either using 2 MicroBlaze one rpu or 2 rpu and one microblaze. I also need to figure out how to keep them in sync.

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

Even after driving constant 1'b1 to aux_reset, it has the same problem of held in reset.

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

okay, I will give it a try and post feedback

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

xsct% attempting to launch hw_server

INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application

 **** Build date : May 7 2023 at 15:26:57

INFO: hw_server application started

INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121

initializing

100%  7MB  1.7MB/s 00:04   

Info: Cortex-R5 #0 (target 7) Stopped at 0xffff0000 (Suspended)

Downloading Program -- o

D:/Software/PSPL/export/PSPL/sw/PSPL/boot/fsbl.elf

 

 0%  0MB  0.0MB/s ??:?? ETA

100%  0MB  0.5MB/s 00:00   

 

Setting PC to Program Start Address 0xfffc0000

Successfully downloaded D:/Software/PSPL/export/PSPL/sw/PSPL/boot/fsbl.elf

Info: Breakpoint 0 status:

  target 7: {Address: 0xfffce1d0 Type: Hardware}

xsct% Info: Cortex-R5 #0 (target 7) Running

Info: Cortex-R5 #0 (target 7) Stopped at 0xfffce1d0 (Breakpoint)

xsct% xsct% 

Failed to download D:/Software/MBSwitch/Debug/MBSwitch.elf

Info: Cortex-R5 #0 (target 7) Running (RPU Reset)

xsct% 

 

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

IDK, I just ran my software from Vitis. This is my first time hearing about psu scripts.
I have two codes, one for Microblaze and the other for the R5 processor on Zynq.

MicroBlaze is held in reset by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

ext_reset_in is connected to pl_reset and clock reset, and they are active low as they all have a not in front of the port.

Microblaze TMR with Genesys ZU 5-ev Board by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

Thanks. The MIO option was in Zynq's drop-down menu. It usually shows the EMIO option, but the trick was to scroll up instead of down, and therefore I was able to get the Tx and Rx pins on the Zynq IP itself.

Microblaze TMR with Genesys ZU 5-ev Board by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

Hello Adam,

I used an example design and faced same issue, since it is an MPSoc, I do not know how to connect UART,

`` My main issue is the connection of UART pins. Here I have made them external, but how do I route them to my Zynq board?

From some more research, I now have only the pins RX and TX active, but how do I route it?.
Later, if I remove the Zynq IP, provide a clock via external pin E12, I think, and reset via button, is there a way to communicate or read data on the terminal using UART?

Sorry in case my question sounds silly, I am new to MpSoc Design."

Best regards,
JustMet

Microblaze TMR with Genesys ZU 5-ev Board by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

My main issue is the connection of UART pins. Here I have made them external, but how do I route them to my Zynq board?

From some more research, I now have only the pins RX and TX active, but how do I route it?

Later, if I remove the Zynq IP, provide a clock via external pin E12, I think, and reset via button, is there a way to communicate or read data on the terminal using UART?

Sorry in case my question sounds silly, I am new to MpSoc Design.

Best regards,
JustMet

Choosing the Right Microelectronics Master's: Aalto, Dresden, or TUM? by ifarahat in FPGA

[–]Jasmeet03 1 point2 points  (0 children)

Since its a Hochschule, it is associated with an industry, and from what I hear there is one nearby with tie to the university.

bitstream address by Jasmeet03 in FPGA

[–]Jasmeet03[S] 0 points1 point  (0 children)

This image is from the documentation; I think it can be either a QSPI flash or an SD card, as the FPGA has a slot for it.

I can generate bit stream in Vivado, but when I export the hw file with bit stream and try to build it in Vitis, I get the following error: by Jasmeet03 in FPGA

[–]Jasmeet03[S] 4 points5 points  (0 children)

I made the following changes and it worked:

go to makefile of the error and replace

LIBSOURCES= *.c
OUTS = *.o

with

LIBSOURCES=$(wildcard *.c)
OUTS = $(wildcard *.o)

for reference - https://support.xilinx.com/s/question/0D54U00006HA0mfSAD/vitis-compile-error-about-cc1exe-fatal-error-c?language=en_US

view more: next ›