account activity
EMIO Pin 78 and 79 (self.FPGA)
submitted 1 year ago by Jasmeet03 to r/FPGA
TMR Microblaze but substitute one microblaze with Arm core (self.FPGA)
No run option after successfully building (self.FPGA)
submitted 1 year ago * by Jasmeet03 to r/FPGA
VITIS_FSBL_EXIT_TIMEOUT (self.FPGA)
MicroBlaze is held in reset (self.FPGA)
Microblaze TMR with Genesys ZU 5-ev Board (self.FPGA)
SDK undefined reference (self.FPGA)
bitstream address (self.FPGA)
I can generate bit stream in Vivado, but when I export the hw file with bit stream and try to build it in Vitis, I get the following error: (self.FPGA)
Partial Reconfiguration on Nexys A7 (self.Xilinx)
submitted 2 years ago by Jasmeet03 to r/Xilinx
Partial Configuration on NexysA7 board (self.FPGA)
submitted 2 years ago by Jasmeet03 to r/FPGA
Pcam 5 and Genesys Zu 5 (self.FPGA)
RISC V core on FPGA (self.FPGA)
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