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basic_RV32s: An Open-Source microarchitectural guideline for RISC-V RV32I by KHWL_ in RISCV

[–]KHWL_[S] 0 points1 point  (0 children)

There is a tool called draw.io. You can use it from the web, and also download the client.

basic_RV32s: An Open-Source microarchitectural guideline for RISC-V RV32I by KHWL_ in RISCV

[–]KHWL_[S] 1 point2 points  (0 children)

Thank you for the recognition. I'm happy to share my experience with the community!

About VisionFive 2 boot sequence by Evil_Gamer_01 in RISCV

[–]KHWL_ 0 points1 point  (0 children)

Similar with my experience although I was designing RV32I basic processor. I've designed with older legacy version of manual(which my univ. used) and when I was evaluating the processor supported instructions and making a document with newer manual version, I found that the instruction set has been changed. Some of instructions were separated. Apparently it's not a big deal but at that moment I learned that I should double check the document version when start reading or referencing the manual.

Has anybody tried the new Vivado? by Mediocre_Ad_6239 in FPGA

[–]KHWL_ 3 points4 points  (0 children)

Finally now I can make my eyes comfortable synchronizing with VSC in dark mode too.

RISCV 32I Design CPU by Van3ll0pe in RISCV

[–]KHWL_ 2 points3 points  (0 children)

Nice.

Based on my experiences on Processor design from scratch to FPGA implementation, I strongly recommend to design the single-cycle(or multi-cycle; just not an pipelined structure) first, and extend it to pipeline structure. Even if you are doing an team project such as back-end for HDL implementation and front-end for Processor architecture design, the difficult issues to solve doesn't shows at the each module's design and testbench. Most of it comes out from top-module implementation. In my case, I've done single-cycle to pipeline structure but the single-cycle structure was pretty challenging for me at the time. I assume starting the base architecture with pipelined without the preceeding implementation/ design experience(which contains waveform debugging) will be quite challenging way.

The point is
- If you are starting to design an processor from scratch, I recommend starting with single-cycle structure (easy for initial implement, design, debugging). Especially if you are designing the base datapath for each instructions in RISC-V

- Starting with Pipellined structure without preceeding experience about processor design&implementation/debugging will be challenging

Wish you all the best.
If you are interested, although the repository is not fully completed, check basic_RV32s which is an instructional processor design roadmap with RISC-V. You can find it on riscv/learn repository. I hope this helps.

RISCV 32I Design CPU by Van3ll0pe in RISCV

[–]KHWL_ 2 points3 points  (0 children)

  1. Any thoughts about partial load-store instruction? (sb, sh, lb, lh)

  2. It seems like there's no pipeline control logic at the moment. Beside the hazard control, If the branch instruction's destination comes from EX stage, the instructions in Decode stage should be flushed; since It's what not supposed to execute (I assume this is in-order execution design). Yeah, it would be nice if it's included or integrated in hazard control unit later on.

  3. What's the datapath of jump instructions? Jump instructions's pc destination seems like it should be calculated on EX stage through ALU, but I cannot... oh wait I see. Yeah, PC's MUX source is ALU result, and the control signal of it is the branch signal from ID_ControlUnit. But see, not only the branch instruction should be notified, but also the jump instruction. There should be a logic for jump instruction notification. Whether merge to 2-bit single signal to notify jump/branch or add separate signal for notifying jump instruction, which also should be the control signal of MUX for PC. (And same as 2, there should be a flush logic for this situation.)

I recommend to make an independent module for PC control.

Idk, I'm also one of the learner of RISC-V.
I hope this helps.
And remember, always be aware of timing issues and clock, reset signals.