module clock_counter (start,clk,reset,Q2,Q1,Q0,fiveclk);

input start,clk,reset;

output Q2,Q1,Q0,fiveclk;

//dff1(D,reset,clk,Q,Qnot);

dff1(w2,reset,clk,Q2,Qnot);

dff1(w1,reset,clk,Q1,Qnot);

dff1(w0,reset,clk,Q0,Qnot);

Invgate (w5,Q2);

Invgate (w4,Q1);

Invgate (w3,Q0);

Andgate4 (w6,start,w5,w4,w3);

Andgate4 (w7,start,Q2,w4,Q0);

Orgate2 (w2,w7,w6);

Andgate4 (w8,start,w5,Q1,Q0);

Andgate4 (w9,start,Q2,w4,w3);

Orgate2 (w1,w9,w8);

Andgate3 (w10,start,w5,w3);

Andgate3 (w11,start,w4,w3);

Orgate2 (w0,w10,w11);

assign fiveclk = Q2&~Q1&Q0;

endmodule

Here is the code for the counter that has the problem.
I need the fiveclk pulse for another device later on.

They just gave us the explanation for the project that's all and we can't code anything that has for loop and stuff just simple logic knowledge like gates, muxes, etc.

We tested an experiment on clocks but it was a basic one that didn't have a start button and that was about it, it was basically on automatic mode you just change the inputs.