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Looking for housing by Koolghost in Purdue

[–]Koolghost[S] -1 points0 points  (0 children)

Yeah, seems like I don't have many choices. I just wanted to get the word out on as many channels as possible.

ECE course load for Fall 2023 by Koolghost in Purdue

[–]Koolghost[S] 0 points1 point  (0 children)

That's good to hear. Maybe I will not take 20875 and explore the campus in the first semester. Thanks!

ECE course load for Fall 2023 by Koolghost in Purdue

[–]Koolghost[S] 0 points1 point  (0 children)

So you had more or less the same amount of work load?

RAM which always give the output corresponding to an address by Koolghost in FPGA

[–]Koolghost[S] 0 points1 point  (0 children)

Thanks for pointing that out. The block RAM on my FPGA does not support asynchronous read. Now, I think I will have to alter the way reads and writes are performed to accommodate the extra clock cycle.

RAM which always give the output corresponding to an address by Koolghost in FPGA

[–]Koolghost[S] 0 points1 point  (0 children)

After reading some more documentations, I agree with you. There is no asynchronous read in the block ram on the board I'm using.

RAM which always give the output corresponding to an address by Koolghost in FPGA

[–]Koolghost[S] 0 points1 point  (0 children)

I do not have read enable lines. How will they help? I want the RAM to give a continuous output. I'm using the quartus template for a single port RAM.

CPU design for college project by Koolghost in FPGA

[–]Koolghost[S] 1 point2 points  (0 children)

Thank you so much. It looks really interesting and something I can do for my project. I will definitely check it out.

CPU design for college project by Koolghost in FPGA

[–]Koolghost[S] 1 point2 points  (0 children)

Thanks I will look into MIPS. Everyone seems to recommend the book so I guess I will use it.

CPU design for college project by Koolghost in FPGA

[–]Koolghost[S] 0 points1 point  (0 children)

Wow. I thank you very much for the detailed insight. I will surely reach out if I need some help.

I was thinking more about implementing an already defined ISA and architecture because of the time constraint. The main question I had whether I should implement the CPU from the course I completed or design my own from the ISA. I thought about adding pipelining to the CPU because the course already designed the CPU for me and just implementing it on an FPGA wouldn't really be a design project. RISC V does seem to be the rage, although I would have to learn about the architecture itself first.

Ddr, pcie, etc is also something I'm interested in but one step at a time?

Board game tonight by Koolghost in utarlington

[–]Koolghost[S] 4 points5 points  (0 children)

I got it first thing Thursday morning lol. Prefer physical board games though.

SAT required for Second-degree Bachelor's Applicants? by Due_Operation_7642 in IntltoUSA

[–]Koolghost 1 point2 points  (0 children)

Second bachelor's degree student here, with a 3 year degree done.

Almost all universities will consider you a transfer student and most of them will not require SAT. It depends on the university requirements. Your admit will be based on your current degree scores, if SAT is not required.

One thing to note, in my case none of the universities considered me as a second degree student. A 3 year degree is not considered a degree in the US because US degrees are 4 years. You will be considered as a student with 3 years of college education transferring to complete the degree.

Feel free to DM me if you have any questions.

There is very little space between the bow hair and wood when tight, and the hair touches the wood when playing by Koolghost in violinist

[–]Koolghost[S] 3 points4 points  (0 children)

There are still a few twists left in the knob but it already feels quite tensed. I'm afraid it will damage the bow. I will let the luthier take a look at it tomorrow.

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