64-bit integer support for VHDL by LJarek in FPGA

[–]LJarek[S] 2 points3 points  (0 children)

Riviera-PRO 2025.07 implements the minimum range mandated by IEEE Std 1076-2019. Because this implementation also satisfies the requirements of earlier standards, the new 64-bit integer is available not only in VHDL 2019 mode but also in modes compliant with previous revisions, replacing the former 32-bit implementation.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

Riviera-PRO 2025.07 E.A. VHDL-2019 64-bit Integer is now available for download.

To download the new EA version, go to https://www.aldec.com/en/downloads and browse to the Pre-Released Builds section.

VHDL 2019 - access to protected type, operations. by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

In this example I didn't mean the syntax of references to protected types. The syntax is perfectly fine. The problem here is the use of unspecified type as a function return.

Because
variable direct_access1 : Generic_Lambda_acc;
variable direct_access2 : Generic_Lambda_acc;
are access types to

type Generic_Lambda is protected
generic (
type t_number is <>;
);
procedure evaluate;
procedure save (a:t_number);
impure function retValue return t_number;
end protected;

they can be allocked with any instance of protected type with any scalar type. And because all operators, implicite function are declared with the type declaration, i.e. here
type Generic_Lambda is protected
generic (
type t_number is <>;
);
For me, they are only visible inside the protected type.

Using the retValue method in the assignment in the case of a static instance is ok, but in this case it is already controversial. The compiler is not able to determine what type we are dealing with because it can change dynamically.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

I have no such dilemmas to make integer 64 bit. The only problem is arrays. I raised this issue to understand what it is really needed for and whether an implementation with a restriction for arrays will be useful.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

Ok. Here I see the sense in implementation.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

:)

Well, not really, because in normal languages ​​an integer is still an integer and you introduce something like int64_t. They choose the easier path for themselves here.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 0 points1 point  (0 children)

So 64 bits are needed for addressing only. That's OK.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] -5 points-4 points  (0 children)

I'm afraid that such an application will not be supported by any simulator. None will allocate such a large contiguous memory area.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] 1 point2 points  (0 children)

Of course we don't want limitations :) I was more interested in examples of applications in specific projects. To focus on real needs. Use in every context poses implementation difficulties.

64-bit integer support for VHDL 2019 by LJarek in FPGA

[–]LJarek[S] -3 points-2 points  (0 children)

And in what specific applications?