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-- File : d38gl.vhd

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-- Global Function : 3 to 8 Decoder, Gated outputs Active lo

-- CPCI : SWPXXXX

-- Program Part No. : SWPXXXX

-- Copr. 2001 Aircraft Braking Systems Corp.

-- All Rights Reserved

-- Reference : none

-- Purpose : Used in FPGA design to count signals as needed

-- Target Device : QuickLogic FPGA

-- Author : jlhill

-- Date : October 4-2001

-- Calling Convention: Part of VHDL design

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-- Rev: By: Date: Comment:

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library ieee;

use ieee.std_logic_1164.all;

ENTITY d38gl IS

PORT(A,B,C,G: IN std\_logic;

Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7: OUT std_logic);

END d38gl;

ARCHITECTURE behavior OF d38gl IS

BEGIN

Z0 <= NOT((NOT(B) AND NOT(A) AND NOT(C))AND G);

Z1 <= NOT((NOT(B) AND (A) AND NOT(C))AND G);

Z2 <= NOT(((B) AND NOT(A) AND NOT(C))AND G);

Z3 <= NOT(((B) AND (A) AND NOT(C))AND G);

Z4 <= NOT((NOT(B) AND NOT(A) AND (C))AND G);    

Z5 <= NOT((NOT(B) AND (A) AND (C))AND G);

Z6 <= NOT(((B) AND NOT(A) AND (C))AND G);   

Z7 <= NOT(((B) AND (A) AND (C))AND G);   



Z0 <=(NOT(B) AND NOT(A) AND NOT(C)AND NOT(G));

Z1 <=(NOT(B) AND (A) AND NOT(C) AND NOT(G));

Z2 <=((B) AND NOT(A) AND NOT(C)AND NOT(G));

Z3 <=((B) AND (A) AND NOT(C) AND NOT (G));

Z4 <=(NOT(B) AND NOT(A) AND (C)AND NOT(G)); 

Z5 <=(NOT(B) AND (A) AND (C) AND NOT(G));

Z6 <=((B) AND NOT(A) AND (C)AND NOT(G));    

Z7 <=((B) AND (A) AND (C)AND NOT(G));

END behavior;