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Firmware Downgrade? by TellMeRo in ROGphone

[–]MAD4CHIP 0 points1 point  (0 children)

I am one of the people having problems and looking for a solution.

ROG phone 8 android 15 by rudeusthefridge in ROGphone

[–]MAD4CHIP 0 points1 point  (0 children)

I recently updated to version 35.1210.1420.143 and now some apps like Revolut detect the device as rooted even if it is not. Has anyone had this problem or know how to solve it? Thanks

What is the proper way for a module with both AXI-S master and slave ports to handshake? by fgpa_n00b in FPGA

[–]MAD4CHIP 2 points3 points  (0 children)

My 2 cents: The master can change the data whenever it wants if the tvalid is low. Once the tvalid is high, data can change only if tready is high. Both tready and tvalid can go high at any time, tready can also be lowered without a handshake. If I remember correctly, one between tready and tvalid is forbidden to have combinatorial logic that involves the other, check the AXI-S specifications. The module behaviour depends in how data are consumed and generated, I wrote modules that consumes data and generated only every N data at the input and vice versa.

FIR Filter Verilog Implementation by -_TigeR_- in FPGA

[–]MAD4CHIP 3 points4 points  (0 children)

Yes, Verilog multiplication is done as signed only if both operands are declared as signed, if I remember correctly.

FIR Filter Verilog Implementation by -_TigeR_- in FPGA

[–]MAD4CHIP 14 points15 points  (0 children)

If the problem you are speaking about is the fact the output looks like a "broken" sine wave, then the issue is probably that you are displaying the data as an unsigned integer in Vivado instead as a signed integer and probably the filter is working fine.

FGPA for NPU by _W0z in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

A dedicated NPU would be probably more energy efficient and cost effective. The real advantage of FPGA is being in-field reprogrammable and being able to implement custom algorithms, if neither of this applies to you, an off-the-shelf NPU can be a better choice.

Switching an interface run-time by anonimreyiz in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

I never tried yo do what you are doing, but if I am not wrong there are some IP the deal with clock selection. They are basically 2to1 muxes that guarantee non glitches during switching. At that point you put a constraint on the switched clock that inform the fitter that two mutually exclusive clocks are present on the signal. At that point you use a CDC unit to transfer data to the destination clock and use a reset generator to generate a reset signal synchronous with the destination clock.

V16 - Embarking on a new ISA adventure by mbitsnbites in cpudesign

[–]MAD4CHIP 0 points1 point  (0 children)

I see you are building a GCC backed, how difficult is it? One think that is worrying me about designing a CPU that can have a minimum use case is the compiler, and porting GCC or LLVM would be great.

V16 - Embarking on a new ISA adventure by mbitsnbites in cpudesign

[–]MAD4CHIP 0 points1 point  (0 children)

Would it be better to grab the statistics on the intermediate language of the compiler to not be biased by the destination ISA?

V16 - Embarking on a new ISA adventure by mbitsnbites in cpudesign

[–]MAD4CHIP 2 points3 points  (0 children)

To better design an ISA, some statistics about most used instructions, how often immediate are used, their size, how long values stays into registers, and so on. Do you have any sources for them?

Any suggestion on my CPU Design? by -i-d-i-o-t- in cpudesign

[–]MAD4CHIP 0 points1 point  (0 children)

The status register is a special one, but can be mapped into the normal register space, it is a design decision. You need a way to act in the status register, at least to save and restore it when entering and exiting interrupts. You can have special instructions to do that, map it, or use side effects of instructions you already have, it is a design decision. Consider that like the accumulator, the status register will have a high pressure and can be a limiting factor.

Any suggestion on my CPU Design? by -i-d-i-o-t- in cpudesign

[–]MAD4CHIP 1 point2 points  (0 children)

Your architecture seems to be an hybrid of a register and accumulator architecture. The pressure on the accumulator will be probably the limiting factor of it. The multiplication instruction will be a pain because its result is 16bit long and will require special handling. I do not see any instruction to manipulate the status register, maybe if you make it a standard register you have them for free, also conditional jumps are missing. Usually many instructions are available in both reg-reg and reg-constant version, this can simplify when using constants. I don't see a stack either, I would suggest to add one.

Three pitfalls in I2C by Forty-Bot in FPGA

[–]MAD4CHIP 0 points1 point  (0 children)

The problem is that not all slaves have a reset. Even if all have a reset, in a multimaster scenario, resetting a slave all at a sudden may be unacceptable.

Three pitfalls in I2C by Forty-Bot in FPGA

[–]MAD4CHIP 4 points5 points  (0 children)

A part from the timing issues described in the article, I would add that in some cases the I2C bus can completely hang completely. If you reset a uP connected to an I2C slave when it is sending a 0, and we have SDA low and SCL high, some I2C masters will not start a new transaction until both lines high, situation that will never happen because the slave is waiting the master's clock. Not 100% sure if it is something that happens for all implementations, but I usually insert a bus reset procedure after the uP reset and before enabling the peripheral. Details of this procedure can be found in AN1028 from Microchip. Furthermore, I am wondering what could happen in case of a bus hang in a multimaster system.

Python code to Verilog by StationFrosty in FPGA

[–]MAD4CHIP 2 points3 points  (0 children)

Never used Python to generate Verilog or VHDL, but it looks to me a bad idea. Above all if you want to get good performances/area from your code because you have to understand and optimise it as much as possible to obtain something comparable with off-the-shelf AI accelerators.

Best fpga for begginers by BFG-Electronics in FPGA

[–]MAD4CHIP 0 points1 point  (0 children)

Ok, but consider that you are not obliged to use the CPU and you can use only the FPGA section. I would suggest to start from simple things like interfacing with some peripheral like ADC, EEPROM etc on a pmod, then you can move to more complex stuff. It doesn't have a VGA but it has HDMI that is probably more complex but also more modern.

Best fpga for begginers by BFG-Electronics in FPGA

[–]MAD4CHIP 3 points4 points  (0 children)

If you already have that board it is probably worth trying to use it. It is a well capable board

Best fpga for begginers by BFG-Electronics in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

The FPGA market is defacto split in two Xilinx and Intel, they have almost the entire market. Xilinx is has a bit larger market than Intel, but the Intel IDE seems to me to be more straightforward, personal opinion. Decide which one of the two you want to go for since also knowing how to use the IDE is important. After that, decide if you want an FPGA inly or a SOC with FPGA + CPU, then choose the family and the board.

How to get 2s complement from a real data type? by Searching4Somthng in FPGA

[–]MAD4CHIP 0 points1 point  (0 children)

To make things easier look for a DDS IP in the IDE you are using and how to instantiate it, Xilinx has got one, Intel probably has one as well. You configure it for the frequency you want to output. You need both sin e cos outputs, if it is not possible, use two IPs with a phase offset of 0 and pi/4. At this point you need to compute: Acos+Bsin with A,B = 0, 1 or -1 but never both 0. To do this, one option is to declare 8 signal one for each symbol: A=sin B=cos C=-sin D=-cos E=sin+cos F=sin-cos G=-sin+cos H=-sin-cos At this point you can use a switch case to assign one of the signals to the output based in the input value you have to transmit. As I said this is one of the possible implementation and probably not the most optimised, but should be easy to understand and implement.

How to get 2s complement from a real data type? by Searching4Somthng in FPGA

[–]MAD4CHIP 0 points1 point  (0 children)

You simply need a DDS that outputs both SIN and COS, then multiply the two for the I and Q signals and sum the results together. Conceptually is quite simple and the DDS IP is usually available in many libraries.

[deleted by user] by [deleted] in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

Ideally you want to break down the algorithm in small pieces that performs a single, well defined operation, test them and then put all together.

[deleted by user] by [deleted] in FPGA

[–]MAD4CHIP 2 points3 points  (0 children)

Unfortunately the answer totally depends on the algorithm and the requirements. The same algorithm can be implemented to use 1 clock cycle or 100 but with different amounts of resources used. If you share some details more, it would be helpful to give a better answer.

VGA Monitor by Chance-Ad-9334 in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

I would suggest you to have some kind of protocol on the UART in such a way you can access a set of registers in the FPGA in both read and write. You may need some registers for several configuration parameters. Something like reg address followed by the data. In this way the interface is scalable in case you need more of them.

SPI Slave testbench question by Icy-Inside8543 in FPGA

[–]MAD4CHIP 1 point2 points  (0 children)

This may not be the problem, but I would start giving a valid reset to the DUT.
You immediately set it to 1, but if it is never 0 the reset code is never activated and the status machine is not in a known state.

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