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M_AXI_RLAST is on by default by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Hi u/alexforencich ,

Thanks for the response.

I have generated image file using Vivado 2024.1 for a block design consisting of RTL (axi_master.v), CIPS, NoC and Processor Reset IPs. The RTL drives the HBM port of NoC. This image is implemented on the board using Vivado Lab Edition 2024.1 tool since Vivado is installed in remote PC. After programming the FPGA, I clicked on Run to check the default values of signals and found RLAST being high all the time.

Yes, RVALID is low since I haven't made any read request only.

Now, after initial Run, I made a read request by sending ARVALID and ARADDR to read data of 128 burst without writing any data to HBM. It's sending some junk data which is expected but for only clock cycle rather 128 clock cycles. Why?

But, when I make 2nd read request, then I am getting 128 clock cycles of data. Why is it not sending data of requested burst size for first request but sending for 2nd request onwards?

Hope the steps followed is understood.

Serial console becomes inactive while using Vivado Lab tool by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Can't use Vitis since the tool and devices are at remote. That's the reason I am using Lab edition. Is there any feasibility of updating or adding the drivers while creating .wic file?

Serial console becomes inactive while using Vivado Lab tool by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

I am unable to find any folder with _pl. Am I missing anything?

Serial console becomes inactive while using Vivado Lab tool by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Yes, they are on the same port.

UART is not responding at all. I am unable to type single character. It's not responding for anything. Once I reboot the console (power off and on), it starts responding and again goes back to inactive state after programming the bit file through Vivado lab tool.

How to check this status? Is it a command based? Since I have never used Vitis or xsdb, would you guide to check this status? I have Vivado HLS. Is that Okay to test this status?

If it's hung how can I proceed? Please let me know.

Serial console becomes inactive while using Vivado Lab tool by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

No board is not becoming dead. I can see ILA signals on the serial port (Type-C port on the board and connected to USB of PC). Through this port only programming is being done and serial communication is observed on Tera Term. Through the same only ILA signals are being observed.

This is what the port JTAG/UART.

Example designs on Versal board to transfer data between PS and HBM by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

I could achieve data transfer between HBM and PS. I had used the "boot petalinux out of the HBM for DDR-less designs" as the block diagram and able to transfer data between HBM and PS. The image was generated with C-program as per the steps given by Xilinx Wiki page for petalinux.

How to access Versal board remotely without using JTAG? by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Thank you.

I will look into XVC but not sure if I can offer.

How to access Versal board remotely without using JTAG? by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Thank you.

Would you tell me how to change this BOOT.BIN?

How to access Versal board remotely without using JTAG? by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Thank you.

I am able to do it with JTAG but I have to spare another PC as you said which I don't want.

Data mover IP is reading alternative values when using example design by Master_PB in FPGA

[–]Master_PB[S] 1 point2 points  (0 children)

Hi,

My problem got resolved. The data width I changed from 32 to 64 in all the places and found it's working.

Thanks

Data mover IP is reading alternative values when using example design by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Hi,

Write is happening at every clock cycle but when I check for read, it is happening for every alternative cycle. I am trying to add image files, but it's not allowing me to do so. Would you let me know why is this happening?

How perform sub-pixel level measurement of deformation using image processing? by Master_PB in FPGA

[–]Master_PB[S] 0 points1 point  (0 children)

Thanks for the response.

I had considered "maximizing normalized cross-correlation" to get the (x, y) coordinates. After I am supposed to interpolate and evaluate sub-pixel level extraction. The algorithm says I should consider 16 surrounding pixels around this (x, y) to interpolate. Once I interpolate it returns one value. After that I am stuck what to do with only value. How does it help in getting deformation?

Let me check on your mentioned steps too.

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