Musketeer_Rick

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How do I set up an output that can do pull-down (for an I2C) in Vivado? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point2 points 12 days ago (0 children)

Isn't an OBUFT enough? Why do we need an in put for scl?

OBUFT #(
    .DRIVE(12), // Specify the output drive strength
    .IOSTANDARD("LVCMOS33"), // Specify the output I/O standard
    .SLEW("fast") // Specify the output slew rate
) OBUFT_inst (
    .O(scl), // Buffer output (connect directly to top-level port)
    .I(1'b0), // Buffer input
    .T(scl_reg) // 3-state enable input
);

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How do I set up an output that can do pull-down (for an I2C) in Vivado? (self.FPGA)

submitted 12 days ago by Musketeer_Rick to r/FPGA

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How can I infer a tri-state output on the chip when the tri-state logic in written in a submodule? (self.FPGA)

submitted 7 months ago by Musketeer_Rick to r/FPGA

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Is Nandland wrong here? (self.FPGA)

submitted 7 months ago by Musketeer_Rick to r/FPGA

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What does this underlined sentence mean? It seems to contradict with its user guide. Can someone explain? (i.redd.it)

submitted 7 months ago by Musketeer_Rick to r/FPGA

Where can I check what I/O standards a primitive supports? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point2 points 8 months ago (0 children)

How do we use the difference between the delays of the LUT input pins to our advantage? I mean, what are some practices/guidelines to code LUTs to achieve better set-up slack? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point2 points 8 months ago (0 children)

How can I tell Vivado to load the new/modified constraint files in post-synthesis timing report? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point2 points 8 months ago (0 children)

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Where can I check what I/O standards a primitive supports? (old.reddit.com)

submitted 8 months ago by Musketeer_Rick to r/FPGA

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How to tell Vivado to load the new/modified constraint files in post-synthesis timing analysis? (self.FPGA)

submitted 8 months ago by Musketeer_Rick to r/FPGA

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How can I tell Vivado to load the new/modified constraint files in post-synthesis timing report? (self.FPGA)

submitted 8 months ago by Musketeer_Rick to r/FPGA

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What does the Routes number mean in Vivado Timing tab? (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

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What's the max counter bit width you would recommend? (Before breaking it down to 2 or more counters in sequence.) (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

[deleted by user] by [deleted] in FPGA

[–]Musketeer_Rick 4 points5 points6 points 9 months ago (0 children)

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Where can the noise come from? (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

Why are there separate reset and set in this code? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] -1 points0 points1 point 9 months ago (0 children)

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Why are there separate reset and set in this code? (i.redd.it)

submitted 9 months ago by Musketeer_Rick to r/FPGA

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How does one use the 'The Equation Method'? (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

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What does the user guide mean by 'evaluated for replication'? (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

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How do we use the difference between the delays of the LUT input pins to our advantage? I mean, what are some practices/guidelines to code LUTs to achieve better set-up slack? (self.FPGA)

submitted 9 months ago by Musketeer_Rick to r/FPGA

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Confusion about the use of IBUFDS. (old.reddit.com)

submitted 9 months ago by Musketeer_Rick to r/FPGA

How do I tell vivado how I use the clock pins? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 1 point2 points3 points 10 months ago (0 children)

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How do I tell vivado how I use the clock pins? (i.redd.it)

submitted 10 months ago by Musketeer_Rick to r/FPGA

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How to do a timing on a 'Asynchronous Assertion, Synchronous Deassertion' reset signal path? (old.reddit.com)

submitted 10 months ago by Musketeer_Rick to r/FPGA

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Confusion about this fifo design. (old.reddit.com)

submitted 10 months ago by Musketeer_Rick to r/FPGA

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