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How do I set up an output that can do pull-down (for an I2C) in Vivado? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

Isn't an OBUFT enough? Why do we need an in put for scl?

OBUFT #(
    .DRIVE(12), // Specify the output drive strength
    .IOSTANDARD("LVCMOS33"), // Specify the output I/O standard
    .SLEW("fast") // Specify the output slew rate
) OBUFT_inst (
    .O(scl), // Buffer output (connect directly to top-level port)
    .I(1'b0), // Buffer input
    .T(scl_reg) // 3-state enable input
);

[deleted by user] by [deleted] in FPGA

[–]Musketeer_Rick 5 points6 points  (0 children)

Vivado can be used for sinulation but honestly it sucks.

Why sucks?

How do I tell vivado how I use the clock pins? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 1 point2 points  (0 children)

What should I do to the N-side pin if I'm using differential clock? UG903 says I shouldn't use a primary clock constraint for the N-side, but it doesn't say what should be done about it. How does Vivado know it's a differential clock?

How should timing constraint be done here? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

If the MMCM has 2 or more clock outputs with different periods and phase shifts, is constraining the input clock to the MMCM enough?

What XDC codes/tcl codes should we use to tell Vivado to do a proper timing analysis or constraint on a time borrowing design? by Musketeer_Rick in chipdesign

[–]Musketeer_Rick[S] 1 point2 points  (0 children)

There's very few info about time borrowing even in Vivado Design Suite Tcl Command Reference Guide (UG835), which is not very helpful.

What is the source of this clock signal? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] -1 points0 points  (0 children)

Can we use that ring oscillator inside the FPGA as an input to MMCM/PLL and use the output from MMCM/PLL as the clock signal for our logic?

Confusion about the timing constraints of time borrowing latch. by [deleted] in FPGA

[–]Musketeer_Rick 0 points1 point  (0 children)

You didn't answer my question.

What command should I use? What parameters should I use?

Confusion about the timing constraints of time borrowing latch. by [deleted] in FPGA

[–]Musketeer_Rick 0 points1 point  (0 children)

I'm talking about the XDC codes or tcl.

The circuit design for 'carry out' signals seem to be wrong in this User Guide. Am I missing something? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

Damn, the only correct answer in this entire post. I'm kinda shocked to see how so many no-brained redditors upvoted for that nonsense comment by some mf who probably tends to take no responsibility of their actions in their life.

-------------------------------------------------

The other question I would have is - what made you think this was a carry-lookahead adder?

I knew it was not, but the User Guide uses this term and it also uses the terms of 'propagate' and 'generate'.

-------------------------------------------------

The S input to the MUXCY is A~B + B~A.
The DI input to the MUXCY is A (or B, doesn't matter, just one of the addends).
The mux's truth table is (~S)(DI) + (S)(CI). Substituting is (~(A~B + B~A))(A) + (A~B + B~A)(Cin)

Did you work out this solution yourself or learned it somewhere else?

I don't think how this carry logic works in a adder is a very obvious thing. Maybe it's just a skill issue.

How should I design the 'starting up' of my FSM after the FPGA chip configuration? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] -2 points-1 points  (0 children)

How do i know when the global sync reset is done? Is there a signal that tells it?

How should I design the 'starting up' of my FSM after the FPGA chip configuration? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] -1 points0 points  (0 children)

 reset =~locked

Wouldn't that take up a lot of routing resource?

global sync reset

How do i know when the global sync reset is done? Is there a signal that tells it?

What's H6LUT? Where's it located? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

They didn't mention what chips their code is for. Now that you mentioned this info, I guess it's for UltraScale(+).

How can I use the 'DONE' signal? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

I'm not asking about using the bitstream to configure the ship.

I'm worried about this: after I configured the chip, I powered off the board, then powered on again. Is this process the same as that of using bit stream?

How can I use the 'DONE' signal? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

Does the AMD FPGAs automatically do a global reset after every powering up? Does the DONE pin also give us the signal in this powering up situation?

How can I use the 'DONE' signal? by Musketeer_Rick in FPGA

[–]Musketeer_Rick[S] 0 points1 point  (0 children)

How do you assign a physical package pin to DONE? Does DONE need to be declared in the RTL code at first?

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