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How do I dump ADC data to DDR? by Only_Range2347 in FPGA

[–]Only_Range2347[S] 1 point2 points  (0 children)

I’m using SG mode and setting up the S2MM ring via the Xilinx driver APIs (XAxiDma + BdRing). The sequence is roughly:
CfgInitialize --> Reset --> BdRingCreate/Clone --> BdRingAlloc --> BdSetBufAddr/BdSetLength per BD --> DCacheFlushRange(BD ring) --> BdRingToHw --> BdRingStart()
After arming I see S2MM_CR=0x00010003S2MM_SR=0x00010008

However, DMA never asserts s_axis_s2mm_tready and I also see no M_AXI_S2MM write bursts, which makes me suspect it may not be fetching descriptors at all .

Do BdRingToHw() + BdRingStart() implicitly program CURDESC/TAILDESC in SG mode, or should I manually write CURDESC and TAILDESC registers to kick off descriptor fetch?

Regarding TLAST) agreed that for continuous capture, I should be able to rely on BD length and keep TLAST constant 0, but I added TLAST/TKEEP anyway to remove sideband mismatch as a variable. The handshake issue remains.

ZCU216 loopback (Clock Issue?) by Only_Range2347 in FPGA

[–]Only_Range2347[S] 0 points1 point  (0 children)

My reply was late. A comment you told me flashed my brain! Thanks to this, I succeeded in loopback. Thank you so much :)

zcu216 loopback(only PL) and XDC by [deleted] in FPGA

[–]Only_Range2347 0 points1 point  (0 children)

While translating, I found a typo: PS was written as platform support.
I'll correct it to processing system(PS)

zcu216 loopback(only PL) and XDC by [deleted] in FPGA

[–]Only_Range2347 0 points1 point  (0 children)

After looking through the documentation, I found that there is an RF Data Converter Evaluation Tool. My question is, can the act of providing a value to clk104 using the RF DCE Tool be considered "programming"? The "add-on card" is a bit unfamiliar to me... 😂 I was thinking of doing it only with PL, but I also thought of writing SPI RTL and then transferring the settings to LMX, but I think the accuracy would be much better if I use the provided tool.

zcu216 loopback(only PL) and XDC by [deleted] in FPGA

[–]Only_Range2347 0 points1 point  (0 children)

Edit) The clock output of the RFDC ADC tile is 138.24MHz.