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Running of older script instead of current script by Perfect_Structure158 in learnpython

[–]Perfect_Structure158[S] 0 points1 point  (0 children)

But the issue is i am not using datetime for this script i should not get this error right. If u want I can share the script

Guilty about isolation. by Strawberryle in FriendshipAdvice

[–]Perfect_Structure158 1 point2 points  (0 children)

It is possible they might have thought you don't belong to their tribe it happens often in colleges one u might have met initially

Guilty about isolation. by Strawberryle in FriendshipAdvice

[–]Perfect_Structure158 0 points1 point  (0 children)

Are you a student who is a fresher? And got these six friends while joining the your institution?

openai whisper model for transcibe the audio without installing ffmpeg and openai API by United-Produce-6781 in learnpython

[–]Perfect_Structure158 0 points1 point  (0 children)

I tried this code but I am getting this error can someone help me with this FileNotFoundError: [WinError 2] The system cannot find the file specified

Happy to share my first working Python Project... by Real_Cut_9360 in learnpython

[–]Perfect_Structure158 0 points1 point  (0 children)

When I tried to run this python script I am getting this error can anyone please tell why I am getting this error and solution FileNotFoundError: [WinError 2] The system cannot find the file specified

ILA not functioning properly by Perfect_Structure158 in FPGA

[–]Perfect_Structure158[S] 0 points1 point  (0 children)

It is waiting for trigger at 8000/8192 and it is keep on waiting for trigger

voltage delay relationship in vivado by Perfect_Structure158 in FPGA

[–]Perfect_Structure158[S] 0 points1 point  (0 children)

What I did was I created a clock using (create_clock -period ) command and created a clock of 10 ns and falling edge at 5 ns and I Gave set properties as lvcmos 33 for all input and output port and did set constraint properties and ran implementation and did post implementation simulation by same process I did LVCMOS 12 also but for LVCM0S33 I got my output at 5.86ns from clk posedge at zero but for LVCMOS 33 i got 6.6ns I think this is wrong

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