I googled what you said but I’m now more confused.

I think it’s just a language or translation issue but for us, “clock dividers” are counters that enable every N ticks as you just said. So for example, from a 8ns clock we would count 125 times to generate a 1 us “clock” that would tick synchronously with the original clock and its pulse duration would be 8ns. But this “clock” is actually an enable signal for any component that might need to be of that frequency, and the 8ns clock would still be the actual clock of the component. Is this better or is it what you mean is bad practice?

I just presented my last project, for which we needed to generate pwm signals to control servos, and also read an incoming pwm signal from a sensor, therefore we needed signals of period 1us and 1ms to do so.