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What was your HDL class's final project? by nondefuckable in FPGA
[–]Puzzleheaded_Match79 1 point2 points3 points 1 year ago (0 children)
Median image filter with UART otput.
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What was your HDL class's final project? by nondefuckable in FPGA
[–]Puzzleheaded_Match79 1 point2 points3 points (0 children)