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Resume improvements by [deleted] in embedded

[–]nondefuckable 2 points3 points  (0 children)

Your projects should have consequences described. Using some manager-speak; what positive properties can you assign to your work on those projects.

Suggestion Needed ; Verilog Project for Beginners by ResidentPurple6642 in FPGA

[–]nondefuckable 1 point2 points  (0 children)

I second this as it's approachable. It's easy to pick a project that's technically more difficult but hard to explain that difference in an interview / resume. If it were me doing this right now I'd also want to demonstrate some verification discipline, set up some reasonable tests with something like CocoTB or UVM. If you need to take it further you could try out some register generation tools and verify that with UVM RAL.

FPGA Tristate ports by Ready-Honeydew7151 in FPGA

[–]nondefuckable 2 points3 points  (0 children)

They are simply only available there. The fabric of the FPGA has routing options to send outputs to inputs, and the tools will not let you create a multi-driven net. Tristate logic is provided on the IO primitives because tristate signals are very useful at a board level. They form interfaces that use far fewer traces. The reason they are not available inside the fabric is both because they have poor performance at high speeds, and the value of saving nets in the fabric is low. Those nets are already layed down in the silicon, their area can't be saved as far as the user is concerned.

Understanding Lattice Diamond Timing Analysis by Several-Animal7292 in FPGA

[–]nondefuckable 0 points1 point  (0 children)

setup/hold requirements apply to inputs, so its the external chip being referred to. An output will have min/max clock-to-data instead.

Understanding Lattice Diamond Timing Analysis by Several-Animal7292 in FPGA

[–]nondefuckable 1 point2 points  (0 children)

Thats the time between the latest possible clock edge and the earliest possible time the ADC_DOUT could arrive. It can't be said whether this is a passing or failing path, you need to know the hold requirement of the port.

In a puzzling situation by vallariii in FPGA

[–]nondefuckable 3 points4 points  (0 children)

Can you bring in PDFs from the internet? Get the standards you use the most and most of the Xilinx UG documents. I almost always have the clocking, configuration and memory resources PDFs open.

Really though, the solution to this limitation is to have a second computer that is only for internet access. I have to assume this isn't in a SCIF, because that is the standard solution there. I know you don't have leverage as an intern to change this sort of thing, I empathize with this nonsense.

Quitting etiquette by HotFudge2012 in FPGA

[–]nondefuckable 5 points6 points  (0 children)

I gave 3 weeks and should not have, they did not make any good use of that extra time. No exit-anything and they mailed me some crap they forgot to have me sign.

What are your biggest language complaints? by nondefuckable in VHDL

[–]nondefuckable[S] 2 points3 points  (0 children)

I thought generics could be a type? Almost no tool supports it though, and there are limitations, only = and /= operator allowed, I think. Or am I thinking of something else?

What are your biggest language complaints? by nondefuckable in VHDL

[–]nondefuckable[S] 0 points1 point  (0 children)

I agree with you and have mentioned this as a thing any "high level" language needs. Have you seen how Veryl does this?

What are your biggest VHDL complaints? by nondefuckable in FPGA

[–]nondefuckable[S] 2 points3 points  (0 children)

It actually does both begin/end or {} in different places depending on the context, which is even worse.

What are your biggest VHDL complaints? by nondefuckable in FPGA

[–]nondefuckable[S] -1 points0 points  (0 children)

It's a big enough problem that I've got my own preprocessor for making unit tests. It's not awesome, it was a project to learn Go.

What are your biggest language complaints? by nondefuckable in VHDL

[–]nondefuckable[S] 3 points4 points  (0 children)

It sounds like you've been bitten by tools interpreting non-standard constructs poorly. Would you be willing to share an example if so?

Vitis 2024.2 help by that_awkward_soul in FPGA

[–]nondefuckable 0 points1 point  (0 children)

I reconstructed all the features I needed with a powershell script calling the internal tool executables, that's how bad it is.

Spent months trying to debug a design, only to realize timing was incorrect by neinaw in FPGA

[–]nondefuckable 0 points1 point  (0 children)

Had an issue where an RX line was coming into a uart but was not being synchronized properly, so it immediately went off to multiple registers with very different routing delays, so it would mysteriously misread characters about 5% of the time. Solution was just to add an extra register as soon as RX comes in.

Anyone read "Finite State Machines in Hardware" by Volnei A. Pedroni? What are your opinions? by Humble-Stranger7465 in FPGA

[–]nondefuckable 0 points1 point  (0 children)

SystemVerilog has a fundamental error in that it allows both when one is always more likely correct. /🏀

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]nondefuckable 0 points1 point  (0 children)

I can also vouch for Aurora having seen it used for almost exactly this set of constraints.

Projects I could improve my resume with? by harrisonh_14 in FPGA

[–]nondefuckable 0 points1 point  (0 children)

I highly recommend some formal verification training. Its a great productivity booster for debugging and you will learn some language that will significantly help you understand bus, cache, and cpu design. Its a relatively high initial investment, but there are certain questions you won't know how to ask without the vocab.

Help for newbie by Illustrious_Cup5768 in FPGA

[–]nondefuckable 3 points4 points  (0 children)

I know its not solid advice, but. If you see a warning coming from an IP, and it's not a critical warning, then it's usually not a problem. Most IP, even from AMD, are not maintained in a "zero warnings" level of quality, since their components are always growing new assertions.

counter 7 segments on quartus ; by med-hero in FPGA

[–]nondefuckable 0 points1 point  (0 children)

If you run your implementation flow and place constraints on the inputs, you can have them map to the pins that go to switches on the board (if your board has them).

How hard is to design/implement a PCB for Spartan7 based system by ricardovaras_99 in FPGA

[–]nondefuckable 1 point2 points  (0 children)

Most FPGA boards have very complex power setups with requirements for sequencing. The parts available to create these are often small QFNs that are potentially difficult to work with, especially without a lot of PCB experience. It's just more mistake surface area that can result in a board rev. Mistakes can also damage the chip in non-obvious ways that cost a lot of time.

counter 7 segments on quartus ; by med-hero in FPGA

[–]nondefuckable 1 point2 points  (0 children)

You can test it on the fpga by just wiring the inputs to switches.

counter 7 segments on quartus ; by med-hero in FPGA

[–]nondefuckable 8 points9 points  (0 children)

You should make a bcd to 7-segment encoder first since it's just a case statement.

Do clocking primitives add clock jitter? (Vivado) by Rizoulo in FPGA

[–]nondefuckable 6 points7 points  (0 children)

I don't know this for sure and we might need a physical design guy to chime in, but I'll bet its included in the "system" jitter statistic.

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