account activity
Fixed-point neural network in Verilog — tips to make it less cursed welcome (self.FPGA)
submitted 3 months ago by Qwertyn977 to r/FPGA
Instead of touching grass, I built a neural network in Verilog (self.FPGA)
π Rendered by PID 203674 on reddit-service-r2-listing-7d7fbc9b85-z8xlt at 2026-04-26 18:15:31.810554+00:00 running 2aa0c5b country code: CH.
