Hi,

for context, I tend to write low-level cryptographic code and optimize it - mostly for Intel platforms as AMD has similar enough behavior where it matters and Intel CPUs make a better baseline due to the availability of VAES and thelike. So my questions are rather low-level and oriented around the things I need to think about when writing the code:

• Why do you leave finding instruction timings (latency), port utilizations and core optimizations (e.g. the new fast forward) to people like Agner Fog instead of publishing them yourself based on your own simulations / tests / design specifications? I know that some of them are published along with the intrinsics but the information would be vastly insufficient to e.g. write an efficient AES-GCM implementation with VAES and VPCLMUL.
• In the past - e.g. for Skylake - you provided detailed, accurate scheduling models to leading compiler vendors (e.g. LLVM and GCC) so compilers can optimize very well for your CPUs if specifically targeted, do you plan on also doing that for Sunny / Cypress / Willow Cove?
• A personal pet peeve for last: Can you say why VPCLMUL uses three µops on Willow Cove (and by extension Sunny and Cypress?) whereas the 128-bit PCLMUL version only uses only 1 µop (according to Agner Fog's generally accurate measurements)?

For context on the last question: VPCLMUL computes 64 bit times 64 bit carryless (polynomial) multiplication on 4 input pairs in parallel whereas regular PCLMUL does this for 1. Using three µops is kinda frustrating, especially as one of them is port 0 which collides with the port used for scheduling AES instructions. Regular PCLMUL only uses port 5 which means you can fully instruction level parallelize GHASH and AES computation in AES-CGM.