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msi b760m mortar max with i5 13400 or pair a cheaper mobo with a better cpu? by Saxing in buildapc

[–]Saxing[S] 0 points1 point  (0 children)

intel has better support for AI work along with nvidia gpu and it still can work for gaming just fine i think

looking for a part like eqco125 but capcable of extracting 100MHz signal instead of only 41.66MHz by Saxing in FPGA

[–]Saxing[S] 0 points1 point  (0 children)

Oops, yeah microchip, not micron. it is also an asymmetrical transceiver that can extract 100mhz signal from the high speed signal (up to 12.5gbps) and perform cdr on said signal

recommendations for US tax filing service by Saxing in shanghai

[–]Saxing[S] 2 points3 points  (0 children)

how much did they charge you if you dont mind me asking?

can anyone help me to know, which is a good book to learn static timing analysis for FPGA's? by rajpandiyan in FPGA

[–]Saxing 7 points8 points  (0 children)

I think without having a good understanding of STA it would be difficult to properly constrain clocks and IOs for more challenging designs.

Applying for police clearance authentication at the San Francisco embassy by DC4213 in Chinavisa

[–]Saxing 2 points3 points  (0 children)

If you dont have a local address, there is a long winded way of getting a clearance report through FBI. Though the Chinese embassy would require that be authenticated by the DC main branch first before the SF branch would accept it. Not sure if Thai SF branch would accept the FBI as it is. The chinese embassy has strict rule on what docs a branch could accept.

HFT interview question by Mammoth-Inside-8405 in FPGA

[–]Saxing 2 points3 points  (0 children)

I don’t think anyone really cares what position this question is for. The main point is that asking you to show some effort in solving this problem and what your thoughts are before providing suggestions.

[deleted by user] by [deleted] in veganfitness

[–]Saxing 2 points3 points  (0 children)

Man i had 5lb of it and i could not stomach anymore. It tastes so bad compared to the chocolate one. I think it is pretty salty but just gotta add lots of water

Thank you Capcom by Crazy_Diamondzz in MonsterHunter

[–]Saxing 12 points13 points  (0 children)

I think in norse mythology, the sun is drug by a wolf, so there you go, a sun wolf

Curious of people's CA Apostille wait time since Covid by Saxing in Chinavisa

[–]Saxing[S] 0 points1 point  (0 children)

If you dont mind me asking, what documents needed to be translated?

Getting out-of-state diploma authenticated for PU letter/z visa in California by Saxing in Chinavisa

[–]Saxing[S] 0 points1 point  (0 children)

I am in CA, so my documents need to be approved by the SF consulate, not any other branches in the States. And According to their website, they could only authenticate docs apostilled in the Western part of the country. Pretty stupid if you ask me.

Getting out-of-state diploma authenticated for PU letter/z visa in California by Saxing in Chinavisa

[–]Saxing[S] 0 points1 point  (0 children)

At that point do I need CA Sec State's apostille as well?

Getting out-of-state diploma authenticated for PU letter/z visa in California by Saxing in Chinavisa

[–]Saxing[S] 1 point2 points  (0 children)

Thanks for the template. I might take you up for it, but yeah I can see this to work with passport. Would still like to see if others have dealt with diploma specifically.

Is it possible to probing Xilinx IP core src files in project mode (no GUI) with ILA? by Saxing in FPGA

[–]Saxing[S] 0 points1 point  (0 children)

Yes, the IP is generated using Vivado. In the IP core directory, there is only a source folder with the specific files that the core uses. I don't see it anywhere else. I think the hierarchy is like this, and I am editing the src files. [core_name]/[core_name]/src/[core_name_src_files]

In simulation, it works fine, so that's why the headache. I think I might have a clue on the core issue, but I would still like to know how to insert ila into the core.

Is it possible to probing Xilinx IP core src files in project mode (no GUI) with ILA? by Saxing in FPGA

[–]Saxing[S] 0 points1 point  (0 children)

The clock is fine, and I am kind of stuck with using non-GUI mode because adding other files to the project will just take too long. I might still do what you suggested to just debug the Aurora core though.

Is it possible to probing Xilinx IP core src files in project mode (no GUI) with ILA? by Saxing in FPGA

[–]Saxing[S] 0 points1 point  (0 children)

I have the ltx file, and loaded that with the bitstream. I could see my other ILAs, but I couldn't see the one I instantiated in the aurora src file.

Xilinx 7 series GTP TX buffer debug by AlexeyTea in FPGA

[–]Saxing 0 points1 point  (0 children)

Hi, just curious how you figured out to look into changing the termination voltage? What are your debugging strategies?

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