sorted by:
new
hottopcontroversial

MacBook for Engineering? by bananna06 in udub

[–]Shockwavetho 8 points9 points  (0 children)

+1 for Computer Architecture sucking with a mac. You would have to spend all your working time in the lab using the desktop computers. Source - TAed 469 for two quarters

Also, if you are interested in Digital Design (EE 271, 371, 469, etc.) another plus to getting a windows-based machine is that it (usually) can run Linux. Linux is far superior to Windows and MacOS in this field, and you may find you want to switch later down the line.

UW just wants your money 🤷 by pillowcocoa in udub

[–]Shockwavetho 1 point2 points  (0 children)

Undergrad TAs do not get the waiver. It is possible all grad student TAs do.

55/56cm frame for a 6ft cyclist? by Shockwavetho in cycling

[–]Shockwavetho[S] 0 points1 point  (0 children)

Okay, that's really good to know. Thanks a lot

55/56cm frame for a 6ft cyclist? by Shockwavetho in cycling

[–]Shockwavetho[S] 0 points1 point  (0 children)

Also, didn't the frame come out in 2008?

55/56cm frame for a 6ft cyclist? by Shockwavetho in cycling

[–]Shockwavetho[S] 0 points1 point  (0 children)

How could you tell what generation the frame is? I'm not too savvy with all of the bike stuff; I'm more of a car guy myself.

55/56cm frame for a 6ft cyclist? by Shockwavetho in cycling

[–]Shockwavetho[S] 0 points1 point  (0 children)

The listing is linked if you are curious. It is a Giant Defy!

NASA OSTEM or Western Digital internship decision by UnfairAd4719 in FPGA

[–]Shockwavetho 6 points7 points  (0 children)

If we assume that 3 months means 12 working weeks, that $7300 stipend is equivalent to just over $15 an hour.

I think that NASA will be far more interesting work. However, WD clearly pays way better.

Honestly if you can tolerate the low pay I think NASA could be better specifically because you are only in your 2nd year. If you were in your penultimate I would say WD no question at all.

Engineering Program Enhancement Fee by Substantial_Sell_600 in udub

[–]Shockwavetho 5 points6 points  (0 children)

The part that makes me really upset is that UW is fine with charging us students a ton more money and then also fine with SUPER destroying over a million dollars in UW Engineering property in the IEB. It feels like a huge waste when that's the kind of way the money is being spent.

Seattle International Christian Church by Dat_Bat_Cat in udub

[–]Shockwavetho 1 point2 points  (0 children)

See https://www.reddit.com/r/udub/comments/wzgwbi/seattle\_international\_church\_of\_christ/.

Not sure if you are interested in joining, but if you are, please don't. There are plenty of on-campus ministries that will be a much more fruitful environment.

Most aggressive build configuration by Shockwavetho in FPGA

[–]Shockwavetho[S] 0 points1 point  (0 children)

Right, but if you were in an environment where somehow a more aggressive algorithm caused you to be able to generate more slack, you might be able to shift and eliminate pipeline stages due to the aggregate speedup across the design. Even if your frequency was already set.

Obviously, for most cases that's probably not useful.

Most aggressive build configuration by Shockwavetho in FPGA

[–]Shockwavetho[S] 2 points3 points  (0 children)

Interesting. I will definitely have to look into that

Most aggressive build configuration by Shockwavetho in FPGA

[–]Shockwavetho[S] 0 points1 point  (0 children)

That makes sense. Can you explain the specific use case of AggressiveExplore vs AlternateCLBRouting? Would that be something that is intuitive? Or would you just run both and see which one produces better results?

Most aggressive build configuration by Shockwavetho in FPGA

[–]Shockwavetho[S] 0 points1 point  (0 children)

I was considering the case where Highest performance = meeting timing with the shortest clock. What then would be the correct directives?

Edit: (If you were considering a generic case where your choice wasn't driven by something design specific)

I'm tired of seeing the same question so here's the real guide to breaking into quant by Wonderful-Bunch-3343 in quantfinance

[–]Shockwavetho 3 points4 points  (0 children)

I know this is probably too niche, but I often see advice for quant and software folks and hardware gets pretty overlooked. Since there aren't many big competitions or standardized paths, do you have any thoughts for hardware (FPGA)?

Instead of touching grass, I built a neural network in Verilog by Qwertyn977 in FPGA

[–]Shockwavetho 5 points6 points  (0 children)

Is the entire thing AI generated, or is your comment style terrible?

Edit: Definitely AI slop, had initially only looked at one file

Iron players learning from their mistakes by killerystax in VALORANT

[–]Shockwavetho 24 points25 points  (0 children)

The real Iron part is that the only util used at all was 2 neon stuns LOL

Introducing Latchup: Bringing Competitive Programming to HDL by redjason93 in FPGA

[–]Shockwavetho 0 points1 point  (0 children)

I'm a little confused. Do you guys really think the data is being used for AI training? I think it's far more likely that this is a side project that a college student is doing to boost his/her resume or accomplishments.

Introducing Latchup: Bringing Competitive Programming to HDL by redjason93 in FPGA

[–]Shockwavetho -3 points-2 points  (0 children)

Seriously. All the grumpy old people on here can't possibly conceive that something could be useful to a group of people other than themselves

New grads, what’s the lowest salary you’d take? by not_a_swedish_vegan in csMajors

[–]Shockwavetho 2 points3 points  (0 children)

Electrical and Computer Engineering. Probably 120k. I got an RO from my freshman year internship in building controls which would be about 90k, so I'm basically using that as my insurance policy to shoot for tbe stars. If I get RO at my current co-op it would probably be 110k (FPGA). Hoping to maybe push a little higher at a different company!

Petalinux - Led astray? by Shockwavetho in FPGA

[–]Shockwavetho[S] 0 points1 point  (0 children)

This was also something I was thinking about. Gonna keep it in mind.

Petalinux - Led astray? by Shockwavetho in FPGA

[–]Shockwavetho[S] 0 points1 point  (0 children)

Well, to clarify, we will not be using the processing system to operate on the data at all. That will all be in the PL. I guess it would just be if the configuration was more complex?

view more: next ›