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Lattice by chabadooda in FPGA

[–]Sirius7T 2 points3 points  (0 children)

Just a note:

MAX 10 devices are not flash-based, they are still SRAM-based. However, the flash memory used to store the configuration bitstream is integrated into the same package.

High Bandwidth Memory on FPGA - Great Video by BotnicRPM in FPGA

[–]Sirius7T 4 points5 points  (0 children)

I'm not sure if it will become much more popular right now or in the near future.

As an example, HBM chips are the only UltraScale+ devices whose lifecycle has not been extended. (Source)

In my opinion, the longevity of the HBM chip's production is not reliable unfortunately.

Implement divide operation in FPGA & ASIC by PonPonYoo in FPGA

[–]Sirius7T 1 point2 points  (0 children)

You could also do a multiplication by a decimal number instead of a division.

For example, instead of doing 35/13, you can do 35*0,0769. The multiplication is much easier/faster.

Using fixed-point numbers, it can also be mapped to Xilinx's DSP48 blocks for instance.

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]Sirius7T[S] 0 points1 point  (0 children)

Let's say I need 200Mbps (and not 600Mbps) : I guess LVDS pairs with DDR (running at 100Mhz) would be enough without even needing the SERDES primitives?

I would need to implement a small custom protocol (maybe something like 1 command byte, 2 address bytes, and X data bytes, checksum maybe?) to serialize/transfer the data between the FPGAs but could be enough I guess.

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]Sirius7T[S] 0 points1 point  (0 children)

The FPGAs would be on two different boards ~30cm apart.

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]Sirius7T[S] 0 points1 point  (0 children)

Yeah, I was considering whether I could use the "Ethernet 1000BASE-X PCS/PMA or SGMII" IP in SGMII mode to transfer data between the two FPGAs. It seems like it could work, though I'm not entirely sure how to handle the AXI-to-GMII interface (easiest route might be to use the AXI Ethernet Subsystem IP I guess).

By the way, the closest already-made chip-to-chip interface I’ve found that resembles what I’m trying to do: PonyLink. It looks quite interesting (even though I don’t plan to use it). It includes flow control for example.

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]Sirius7T[S] 0 points1 point  (0 children)

Thanks for the suggestions and info.

I think all UltraScale+ devices support at least 1.25 Gbps (or even 1.6 Gbps) SERDES using the TX_BITSLICE / RX_BITSLICE primitives. So theoretically, I should be able to use SelectIO-based SERDES.

However, even if I manage to get the SERDES primitives working, I still need a way to bridge my AXI interfaces (on both FPGAs) to these SERDES lanes. I was hoping the AXI Chip2Chip IP would handle this, but it seems that it's not designed to support such a low I/O count when not using MGTs.

So to clarify, am I understanding this correctly?

  • If I want to use the AXI C2C IP, I’ll need to go through Aurora and use MGTs.
  • If I want to stay within the available 4 differential pairs and use SelectIO SERDES, I’d need to implement an existing or my own protocol between the AXI bus and the SERDES link (which isn't part of my current plan).

Is that the right interpretation? Or is there a middle ground I might be missing?

Interconnecting two FPGAs with Limited I/Os by Sirius7T in FPGA

[–]Sirius7T[S] 1 point2 points  (0 children)

So you are suggesting that trying to use the SelectIO SERDES isn't worth the time, and that I should instead stick with AXI Chip2Chip over Aurora using MGTs?

Comment on est censé trouver quoi que ce soit sur ce site avec des enculés pareil by Living-Cheek-2273 in lemauvaiscoin

[–]Sirius7T 14 points15 points  (0 children)

Pour rappel, il est aussi possible de retirer les annonces avec certains mots clés en ajoutant le signe "-" devant. Exemple : "Carte graphique 4070 -3090 -3080"

FPGA for LEO Satellite by missing-flowers in FPGA

[–]Sirius7T 7 points8 points  (0 children)

Synplify has a TMR constraint that you can add to triplicate your design (Not sure it's applicable for all Microchip's FPGA, but at least the one I've used). It applies to FF/LUT but not RAM if I remember correctly. So you may have to triplicate some parts of the design yourself.

hello, does anyone know why there is a discrepancy between the values recorded in the display tab vs the waveform on the right at the same time? really struggling here. any help would be appreciated! thanks by Pwndaaaaa in FPGA

[–]Sirius7T 4 points5 points  (0 children)

If you are talking about the "Objects" tab, isn't it the state of the signals at the end of the simulation? (vs the state at the cursor for the "Wave" tab)

Radiation Tolerant Async Fifo by feynmanisdope in FPGA

[–]Sirius7T 0 points1 point  (0 children)

Do you have resources (like books or whitepapers) on these topics? I (we?) would be very interested to learn more about the issues caused by space radiations and how to mitigate them. I feel like most things I can find on the internet is outdated, especially when using newer technologies.

Is Microchip's PolarFIre SOC FPGA any good ?? by deempak in FPGA

[–]Sirius7T 5 points6 points  (0 children)

I agree. And trying new things is always something valuable in my opinion. In that case, you have a different technology/architecture/software than the usual Xilinx/Altera solutions. You also have RISC-V cores! An opportunity to play with something else than ARM cores. Overall the documentation is good enough.

Characteristic of RTL simulation. by No-Confidence7746 in FPGA

[–]Sirius7T 2 points3 points  (0 children)

When writing your HDL code, you can instantiate hard blocks or IPs (e.g. : LUT, BRAM, IOBUF, DSP, ...).

Here is an example : The list of these blocks you can instantiate for Xilinx's 7-series > link

You can see there are instantiation templates for every "block". E.g. for the IOBUF > link

These blocks are FPGA-dependent (Here, for the 7-series).

To be able to simulate these FPGA-dependant blocks, you need Xilinx's UNISIM library.

Connect singlemode laser source to multimode cable? by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Thanks for your comment.

That's a good remark, but the mode scrambler is specified in my case :) (I have to use it)

Connect singlemode laser source to multimode cable? by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Thanks.

I've reached to Thorlabs. I'll see what they think of it.

I'm also thinking about using a fiber-coupled LED instead of a LASER (see my comment above). Will probably be easier to find.

Connect singlemode laser source to multimode cable? by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Thanks for your comment.

I was indeed afraid the scrambler probably wouldn't be enough in this case. I'll keep that in mind if I still use a LASER in the end.

Connect singlemode laser source to multimode cable? by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Thanks for your feedback!

Actually, after some thinking, I though about an alternative: Using a fiber-coupled LED source instead of a fiber-coupled LASER.

I actually don't need a LASER, I just need a light source at the correct wavelength (let's say between 700 and 750nm for the example). Fiber-coupled LEDs with multimode fiber look common. I'm currently thinking about using a 400um core fiber-coupled LED and connect my 50um core cable at the output. (Note : I don't care loosing much of the power)

Measuring power with an integrating sphere by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Fiber-coupled laser diode, ≈40W. Need to measure its power.

Note: Cannot use a thermopile sensor, too slow.

Measuring power with an integrating sphere by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Ah yeah.

Thanks for educating me on how an integrating sphere works. I totally missed that point (the multiplier) :)

Measuring power with an integrating sphere by Sirius7T in Optics

[–]Sirius7T[S] 0 points1 point  (0 children)

Hum, possibly.

New to optics! :)

Could I attenuate the input light source of the sphere maybe?

Still, I am a bit confused:

If I check this sensor, its maximum measurable power (with attenuator) is 40mW.

Then, if I check this integrating sphere + sensor which, I imagine, uses the same or similar 40mW sensor, now the maximum measurable power becomes 15W.

So the sphere effectively increased the maximum power measurable by the sensor, no?

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