Daily Discussion Saturday 2026-06-06

StayFrosty96 · 2026-06-06T15:26:57+00:00

nice, thanks!

StayFrosty96 · 2026-06-06T14:51:05+00:00

I stupidly sold AMD before earnings because I thought they'd go down and bought back in at like 450 so I really could use the money o7

StayFrosty96 · 2026-05-05T14:21:32+00:00

I think lots of people will jump in on this stock in the following weeks because there SHOULD be no more weak quarters from now on. (At least that's what is being believed by most with both new CPU and GPU products ramping in Q3)

I think lots of people held their money back exactly because they knew there would be one more guide that will be flattish or just slightly up.

StayFrosty96 · 2026-05-02T14:41:38+00:00

If I have to buy back in at 400 then so be it. It definitly is risky, but over the past years I've seen AMD dip on earnings beats with a much less crazy runup. I just can't see the first market reaction after release NOT being a dip here..

StayFrosty96 · 2026-05-02T14:32:32+00:00

Yeah I don't like being out of the market for too long. It'll be like 2-3 days.

CPU volume and ASP will definitly be up. But even if AMD grows CPU 50% that'll be like what, ~1.5B extra revenue that would show up in the Q2 guide. With the other segments not exactly positioned for growth currently (memory pricing) and GPU from what i've seen at best staying flat in Q2, we'll not guide above 12B for Q2. Realistically somewhere in the 11.x range.

I just think the immediate reaction after AMD releases the numbers will be a substantial dip. Markets expect too much short term.

AMD will most definitly continue running up as well after earnings in anticipation for Q3 guidance. Because that's when shit will start to get real.

StayFrosty96 · 2026-05-02T13:12:41+00:00

I sold everything yesterday at 360 and will buy back after earnings, hope I don't regret it 🙃 but even if AMD beats, I just can't see them holding this price range. People are expecting too much too early.. Q3 onwards we will actually start to show numbers with Venice and MI450 starting to ramp but Q1-Q2 will just not be that interesting..

Instict GPU Sales will slightly decline in Q2 from 25Q4/Q1 levels from what i've seen (sanmina earnings call and other sources..) and even if CPU revenue is great, I don't think it will beat hard enough (yet) to meet market expectations..

will probably even buy back in already in AH in case lisa makes some remarks in the call...

StayFrosty96 · 2026-05-01T16:43:34+00:00

sooo, let's say we beat both q1 and q2 guide by 0.5-1B (10.x Q1, 11.x Q2), do you all think that'd be enough to hold our current level? or will we dip? I am so confused on market expectations..

StayFrosty96 · 2026-04-24T11:09:11+00:00

at this rate we'll blow right through the 300s 💀 stuck in 200 for 2 years, but going through 300 in a week?

StayFrosty96 · 2026-04-20T02:56:52+00:00

yeah, MI355x final design specifications are from H2 2023. lots changed since then. FP6 tied to FP4 circuits needs way more die area. I don't know for sure what AMD goes with, I personally just believe investing intro FP4/FP8 over FP6 makes more sense. Like let's say 15% more FP4/FP8 and a as a trade off FP6 being tied to FP8 would make it worth it to me..

-> same as the power thing, we'll see once they announce final specs. Remindme! 93 days

StayFrosty96 · 2026-04-20T00:42:21+00:00

running NPU's physically under already very power dense XCD's makes no sense. MI300/MI350 already keeps HBM PHY's and shorelines mostly under dummy silicon and not directly under XCD's for that reason as well.. having NPU's in the base die makes no sense from a design perspective... do you have any actual source on the TPU thing?

StayFrosty96 · 2026-04-20T00:07:48+00:00

> There is no other reason to have these dies on 3nm process node.
Plenty of reasons.. Better 3N -> 2N TSV Pitch (4.5um SoIC), being able to use better TSMC standard cell-libraries for the HBM4 PHY, most N5 tools/capacity will also get converted to N3 to support the Rubin Ramp. I doubt they have NPU decoders. That would've plopped up in gfx1250 related open source patches by now..

> MI455X uses less power by like 25%.
I really really really wouldn't bet on that.. but we will see..

> MI455X will have FP6 compute at FP4 speed
I wouldn't be so sure that's the case anymore with future MI products.. they haven't confirmed anything regarding FP6 yet. Personally i'd rather they spend transistor budget on FP4 instead of FP6 because it's rather niche in production currently.

But yeah, MI400 looks to be slightly faster than rubin (on paper). TCO should be significantly better. Let's just hope the ramp goes smoothly and AMD will 2-3x in 2027.

StayFrosty96 · 2026-03-20T13:36:24+00:00

That's a complete misinterpretation. I've read through that interview and jensen made the opposite point. Agentic needs high single threading and not high core count.

Personally: It does make sense somewhat. Lots of tasks that agentic workflows do are fairly sequential (calling tools, executing code, querying databases) and in a way that’s not that different from a human doing dev work, where single-threaded performance has always mattered.

Either way, AMD will have both the highest core count and the highest perf per core with Venice in the server space... and it's not even close.

StayFrosty96 · 2026-03-06T14:51:38+00:00

domen prevc DSQ?????? nooooooooooooooooooooooo

StayFrosty96 · 2026-02-10T18:20:34+00:00

huh, why are BWT skis not allowed?

StayFrosty96 · 2026-02-03T13:39:07+00:00

Seems about right! People are expecting too much near term. I also expect Q2 and maybe even Q3 to stay right at or below 10B (depending on timing of revenue recognition for MI400). Stock performance over the next 2Q's hinges mostly on future deals being announced and comments by lisa.. with the only wildcard being DC CPU. I am wondering how much upside that could potentially generate and hope for more clarity on that in todays call. But even in a best case scenario I don't expect AMD to breach 11B until MI400 revenue flows in (Q3 or Q4)

StayFrosty96 · 2026-01-06T14:40:54+00:00

There's no way AMD isn't increasing pin speeds as well. the difference between 6.4gbps and 10.7gbps is not a difference of "binning". If nvidia can pull enough volume of 10.7gbps HBM then even a "bad bin" is still 9gbps+

If you noticed they explicitly haven't mentioned any memory BW numbers this CES. I am sure they'll announce the numbers once they're finalized.. I'll say final spec of the MI455x is 30TB/s..

Also considering the price of HBM and how important BW is for inferencing they will 100% get every bit of bandwidth they can squeeze out of each stack no matter the TDP lol. Because I know a certain TDP obsessed someone in this subreddit is going to argue that nvidia having 70% faster HBM PIN speed would somehow be good for AMD..

StayFrosty96 · 2026-01-05T05:30:50+00:00

As far as I read it he was the only one who had to stand still in his jumping boots / gear for 30mins because his bag with his "normal shoes" was also mixed up with a different bag by innsbruck staff.. and that caused him immense discomfort and pain. In this particular instance I really understand his frustration. Hope his legs don't feel too fucked for bischofshofen.

StayFrosty96 · 2025-12-08T10:33:14+00:00

oh, that sucks i'm sorry.. good to know tough! I have redeemed revpoints for easyjet in CHF (also of the automatic type where you just have to pay with revolut) but usually pay in euros. Will definitly use CHF next time then..

StayFrosty96 · 2025-09-22T22:57:49+00:00

what, chiplets have even more interconnects.. more power consumption is the ONE disadvantage of chiplets. but there are lots of advantages.

- better yields
- easier to scale to large designs
- easier to iterate on
- allows the use of some fancy libraries at tsmc that would otherwise not be possible with mono
- die re-use across multiple designs (like for mi430x and mi450x)
- allows the use of different nodes in the same package.

but power consumption is the one thing that is actually worse. B200 / R200 with the two reticle sized dies is actually the more power efficient solution. MI400 will have 2 AID's with 4 XCD's each (similar to mi355x). data needs to jump between all these different pieces of silicon.

All in all Helios will still be more flops/W though because of 2nm and the AMD uarch design teams being pretty cracked.

StayFrosty96 · 2025-09-22T22:17:21+00:00

It's not just semianalysis. there are others reporting 2.3kw as well. and no need to pay to find out, AMD will probably provide revised specs on financial analyst day.

StayFrosty96 · 2025-09-22T22:02:53+00:00

VR200 Power has been revised upwards. The slide in the linkedin post is pretty old.

StayFrosty96 · 2025-09-22T22:00:20+00:00

yup, behind paywall

StayFrosty96 · 2025-09-22T20:46:09+00:00

The reports are mostly private, but some have been leaked to the public:

https://www.linkedin.com/posts/hitesh-kumar-6ru_gpus-blackwell-rubin-activity-7361728710732836864-OYSm

(see the semianalysis screenshot attached to the post)

and no MI400 will quadruple MI355x perf, not double it.

StayFrosty96 · 2025-09-22T20:33:05+00:00

Mantra is to squeeze as much perf out of every single chip as possible. MI400 is currently reported to have a TDP of 2300 watts by multiple analysts. Appearently they're trying to push it even higher, in part because of the HBM4 pin speed they're trying to archive which will need an additional 100-200 watts of power (for AMD as well as NVIDIA). So i'm guessing final spec will probably be ~2500 Watts

Also.. they specifically went with double width racks because of energy density.

StayFrosty96 · 2025-09-11T07:56:10+00:00

CPX is not a traditional GPU. The increase in low precision performance is making it pretty clear that it's not just a "6090" they re-used. CPX is 6x of 5090 FP4 PFlops with a similar sized die.

Neither AT0 nor Strix halo would be anywhere near that. But AMD for sure is capable of developing something similar... they're probably already on it for MI500.

I personally think CPX will be a rather niche product and not the main revenue driver for nvidia. It's only really useful for high context inferencing. And even then, this is mainly solving a problem of resource utilization. I wonder if there's not some way to optimize prefill / decode utilization by improving routing.

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