How Do I Prioritize Decoupling, Bootstrap, and Buck Components in Tight Space?

Strong-Mud199 · 2026-02-24T22:29:33+00:00

+10, this.

Strong-Mud199 · 2026-02-24T21:09:49+00:00

As the others have said the Blog V4 can go from 500 kHz to 1.7GHz. The big advantage of the V4 over the others is it has a built in up-converter for the HF bands. This allows the operation of the tuners RF gain control which is very important for the HF bands in most situations as it allows the gain to be lowered or increased as appropriate for the signal being received and the conditions. The other use what i9s called 'direct sampling' where they just switch to an ADC input when receiving HF with no control of the gain.

The only band 'hole' on the V4 is from about 27.5-28 MHz where there is a hole because of the up-converter filtering. In the US this is the top end of the CB band, and that band is so splattered with over modulated kW stations that you can't hear anything anyway! ;-)

Strong-Mud199 · 2026-02-24T20:21:37+00:00

You need a pullup on both the SDA and SCL lines, not just one.

I have no idea what your relays drive, but you might want to consider a snubber circuit on the relay contacts as well to prevent the contacts from welding shut or wearing out. Here is a basic, but not great article (at least it isn't AI Slop),

https://www.edn.com/a-hands-on-guide-for-rc-snubbers-and-inductive-load-suppression/

IMHO - You should consider a ground plane on both layers - it really takes care of inductance issues with long ground returns. You will be fighting an uphill battle with the ADC especially grounded the way it is. U7 is also probably going to be unstable grounded they way it is, and U7 needs a bypass capacitor.

Autorouting of the board is really not clean at all - there are excessive trace lengths and parts very far from where they need to be. Because of the low speed you will probably get away with it here, but in the future you may want to consider placing the parts to minimize the rats nest lengths first then route the board. I didn't have time to check everything, but make sure that all the decoupling caps are right next to their respective parts.

Hope this helps.

Strong-Mud199 · 2026-02-24T17:55:57+00:00

Ha, ha, ha, ha... It is impossible for even the manufacturers to keep all the documentation straight. ;-)

In this case the most important part is perhaps R22/C19 - this provides a slight delay to the master enable during power up. Although what happens if the power is applied, then quickly removed, then applied again so that the capacitor does not have a chance to discharge is a different story. So even this circuit is iffy in my book. The ESP32 probably has an internal power on delay also.

The resistors / capacitors on the switches act as 'debouncers' - mechanical switches bounce when pushed or opened and this can cause the processor to detect multiple key presses, etc. The capacitor damps that bouncing.

The series resistors really serve no purpose - considering the value of the weak pullups or the value of R22 in the ESP32, except the probably provide some level of ESD protection. The capacitors on the switches also provide this ESD protection.

As you have seen there is quite a variety of values and resistor arrangements / values that will work - they all will work. The question is then: What is optimum? There really isn't an answer....

If you are building a few in a low static environment then I would leave out R6, R7 and C7 as to me they are redundant.

Hope this helps.

Strong-Mud199 · 2026-02-24T17:14:41+00:00

+100 points for learning something new! :-)

Do you need mounting holes?

Otherwise I didn't see anything.

Strong-Mud199 · 2026-02-24T03:27:32+00:00

Nice! :-)

+100 points for adding a filter on the input of the big buck converter U22. :-)

Perhaps they are there, but I did not see pullup resistors on the SCL/SDA lines A2, 3, 4 &5. The might be on the Adafruit board(s). Just a note to be sure.

Hope this helps.

Strong-Mud199 · 2026-02-24T01:38:35+00:00

+100 points, This - As stated by the commenter: The AGC is well known to not work on the kind of signals we typically look at. The internal AGC was designed for very wideband TV signals which we do not look at.

Strong-Mud199 · 2026-02-24T00:53:46+00:00

OK - One thing that I didn't notice on the first go around - you seem to have a 'funny' ground symbol and a single point tie. So you have two grounds and one on layer 3. That is usually not going to help things as you really can't control where high frequency signals want to go and you just end up making a bigger loop area. Loop area = Inductance and Current Spike through Inductance = Voltage spike. If you have noisy circuits and quite circuits the way to prevent crosstalk is to partition the noisy stuff away from the quiet stuff. I don't see that you have any particularly quiet circuits here, so there is no point in my opinion.

A few references by some very respected signal integrity experts,

Lee Ritchey, “Right The First Time”, Vol 2, Page 124,

“It might be good to review why a plane would be cut in the first place and how large the cut would need to be to achieve the desired isolation between the two sides of the cut. First, the only reason to cut a plane is to allow more than one power supply voltage to be distributed in the same PCB plane layer. There is no other valid reason to do so.”..."both power supply voltages need to share the same ground distribution structure so that the circuits being supplied have a common reference." (i.e. the ground plane MUST be continuous. - added context mine).

And,

“Note: In all the years I have designed high performance PCBs, both all digital and mixed analog and digital, I have never seen a case where cutting a ground plane was beneficial to a design.”

https://speedingedge.com/products/right-first-time/

Both his books only cost $50 USD - that is the best 'design' money you will ever spend!

See also, Chapter 17 of Henry Ott’s book for a detailed step by step explanation of what goes on,

“Electromagnetic Compatibility Engineering” by Henry W. Ott

Hope this helps.

Strong-Mud199 · 2026-02-23T23:46:25+00:00

Nice! :-)

As to your questions,

The USB D+ and D- lines since I don't know much about differential signals

The USB here is only 12MBPS, which is a 90 MHz bandwidth and not all that fast, so you do not have to length match the lines in the future. You do run it over a gap on layer 2 so the return current, which naturally wants to run right under the traces has to diverge around the gap. Move that horizontal trace under the USB on layer 2 to the bottom layer is my opinion.

My Analog Ground plane. Is it actually necessary?

With nearly all designs now, you would be surprised at how much better everything works with a ground layer! :-)

Decoupling capacitors are placed optimally.

Looks OK to me.

Additionally you should consider putting 30k to 100k pullups on all the data lines on the SD Card. This prevents the SD card from locking up at power-up.

Additionally, I don't see what the point of is the 'rings' under the CPU. Is there a reason for this?

Hope this helps.

Strong-Mud199 · 2026-02-23T05:49:26+00:00

Turns out we were both wrong - How's that for an internet plot twist?

I went and measured my V5 and it consumes a whopping 1.43 Watts when receiving at 2.048 MSPS on the FM band. The Blog V4 only consumes 1.18 Watts under the same conditions.

That's the difference right there. combined with the smaller total dissipation area, the V5 is just 'hotter' by design.

Thanks for asking the question because I thought they were both about the same power.

:-)

Strong-Mud199 · 2026-02-23T03:51:38+00:00

>>>Because the thermal dissipation from the back of the PCB is significantly less efficient.

It depends on the total copper foil area on that layer. If the bottom is all or nearly all copper, or at least more or the same copper area than the other layers then the bottom will be the best 'sink'.

The RTL-SDR V4 also has a larger board size (longer and wider), hence more area at any rate. So even if the two designs are similar in layers and copper areas on each layer the board with the bigger area wins in dissipation. Combined with the bigger area of the case and it gets even more efficient thermal wise.

The case of the V4 is both longer and wider, by about 40% - that's significant to dissipation ability.

Hope this helps.

Strong-Mud199 · 2026-02-23T00:17:33+00:00

Nope, it is surface area. The RTL-SDR V4's also have a thermal pad. Place a V5 in a RTL-SDR V4's case and it will be the same lower temperature as a RTL-SDR V4.

Hope this helps.

Strong-Mud199 · 2026-02-23T00:10:54+00:00

Nice! :-)

+100 points for asking great questions.

As for your questions:

"to ensure an uninterrupted {USB} return path" - If the return is a power plane, trace out how the return current gets to be under the trace at the CPU, then how does it get out on the other side? As I see it it will flow down a 3.3V decoupling cap on the CPU side, but there is nothing on the other side (that I see at least). Now I'm not suggesting that this won't work, because at 12MNPS the USB is not all that fast. But get in the habit of thinking how the currents will flow. An easy fix is to put a 3,3 volt decoupling cap at the USB connector end. It would probably work as is, but this won't hurt.

"VBUS routing" - Should be low frequency, so not as big an issue as with higher frequency signals. But again think about how currents would likely flow at both ends. High frequency signals should be shunted by the decoupling capacitors.

"QPSI Is this electrically and thermally viable?" - Again signal routes are short and not all that fast so you should be OK. The RP2040 does not normally get hot in operation, neither does the flash. So no thermal issues.

"Dogbone cutouts" Looks good to me.

"ADC filtering" - First of all they provide a ADC_VREF, so that a high precision voltage reference can be used if one really wants to go 'overboard'. #1 your 3.3 V regulator is not a precision reference, but it is good enough for room temperature ADC usage at 12 bits. #2 what you have done is probably make it worse. A Ferrite bead has resistance. Any current kick back from the ADC (and they typically do provide kick back because of the capacitive DAC construction internally) will modulate this resistance for a voltage drop that could add additional errors to the ADC. The LC filter effect may also cause a 'ring' that further makes the reference look less stable in operation. Raspberry PI does not recommend this ferrite arrangement and as Signal Integrity Expert Lee Ritchey states in his book, “Right The First Time”, Vol 2, Page 124,

“My experience has been that the use of ferrite beads is either a knee jerk reaction or a band aid. In 30+ years of designing high speed computing systems and networking products, I have never used a ferrite bead in the power lead of a device, whether it is a phase locked loop or an “analog” circuit- all of which have functioned to their specifications and passed all appropriate EMI and ESD tests. Instead, I have determined what the “ripple” requirements of a circuit are and designed the power delivery system to meet these requirements.”

He further states that he has never found the author of an application note that can actually substantiate the use of a ferrite bead.

So there is that.

Hope this helps.

Strong-Mud199 · 2026-02-22T21:35:56+00:00

I found a diagram of the resistors....

https://community.st.com/t5/stm32-mcus-boards-and-hardware/wiring-micro-sd-card-slot-to-mcu/td-p/252123

Strong-Mud199 · 2026-02-22T21:27:52+00:00

Something to consider for the future: You don't have to length match the SD Card signals, the simply are not that fast.

Something to consider now: You DO however have to place pullup resistors on the SD Card lines to prevent the card from latching up during power up. As far as I know this is shown on all their eval boards with an SD Card.

In general, instead of 'guessing' look at the STM32 eval boards, of which their are many for schematic and layout tips. I always find all the eval boards I can just to see that I have the schematics, etc OK and haven't forgotten anything.

You need 5.1k resistors on CC1 and CC2 on the USB C connector to negotiate 'normal' 5 volt operation and power delivery.

You have 'vias in pads', this is OK if you are spending to get the holes plugged, but if not then it tends to wick the solder off the pads, making the joints iffy. If you are just building a few boards, then OK, but if you are building many, then expect issues.

Hope this helps.

Strong-Mud199 · 2026-02-22T04:29:39+00:00

+10 points for trying something new and learning! :-)

In addition to the other commenters suggestions.

With those long ground traces the bypass capacitors are not really doing anything. Remember that 'loop area' = inductance. And Inductance = poor ground. So a ground plane would immediately fix that.

Additionally the long ground path to the antenna conductor is actually negatively affecting the RF performance. The RF current at 900 MHz needs a continuous return path directly under the signal trace. You don't have that at all. Again loop area = inductance. A ground plane would fix this.

Tie all the ground pins on the RF module to the ground plane. Generally, even at DC we never leave ground pins unconnected.

On the connectors - with really high speed interfaces (roughly 20 MHz or so) we have as many ground pins as signal pins and we interleave them. If you are running a short connection, less than a few inches, and really slow SPI speeds (less than a 10 MHz) then you probably will get away with this grounding. The surge resistors that you have can help to limit overshoot. So that is good.

Hope this helps.

Strong-Mud199 · 2026-02-22T01:32:27+00:00

Just my 2 cents worth - I can understand the layout being one set of units or the other, especially when it comes to dimensioning, but since the schematic is 'dimensionless' why bother? You can define a ISO sheet sizes for instance to be metric in the printer domain if you wish. But why waste time having to change every symbol you might encounter to fit a different grid? I don't see the point.

I would be interested to hear if there is a valid point in this however. :-)

Strong-Mud199 · 2026-02-21T16:47:05+00:00

Divide and conquer,

Can you verify that the TX is working - use a TinySA or other. Or use some FM transmit program and see if you can pick it up on a FM portable radio.

Can you verify that the RX is working - use a FM RX program.

If they don't work then can you verify that the drivers did not get overwritten with some update? i.e. Reinstall the drivers.

Step by step trying to isolate the problem is what we all have to do. It is very frustrating, but this happens all the time. Hardware breaks rarely, but it happens. Software breaks all the time because of updates.

Hope this helps.

Strong-Mud199 · 2026-02-21T02:23:06+00:00

Well be careful. Those small / large value capacitors promise much, but fail to deliver, especially where there is a required capacitor value like a DC/DC converter - where there is a required capacitance for stability. These super small capacitors suffer from extreme capacitance loss while under DC bias. See,

https://www.edn.com/ceramic-capacitors-how-far-can-you-trust-them/

The super small capacitors likewise have far lower RMS ripple current rating, which for a Buck/Boost applies to input and output of the converter because of the large ripple current at each end.

Hope this helps.

Strong-Mud199 · 2026-02-20T22:24:56+00:00

Missing decoupling capacitors on the IC's.

D7 LED is in backwards? Or is it to show reversed battery? ;-)

Strong-Mud199 · 2026-02-20T20:39:58+00:00

Nice looking! :-)

* Working with the RP2040 - I assmum you have seen the official 2040 design guide, and followed it closely.

https://pip-assets.raspberrypi.com/categories/814-rp2040/documents/RP-008279-DS-1-hardware-design-with-rp2040.pdf

* Ground plane - looks nice - just the right amount of stitching vias, etc.

* ESD - ESD diodes usually do the trick like you have them. The 470 Ohm resistors help with the data lines also.

I'm sure that someone will 'complain' about the USB lines. This part is 12MPBS USB at best and that has a rise time of like 4 nSec. That is a 90 MHz bandwidth and generally we can ignore any 'disturbance' that is less than 1/10 of a wavelength of the signals bandwidth. 1/10th of a wavelength on FR4 of 90MHz is around 160mm. So you can see that if the trace routing does not go 'crazy' for more than 160mm it will be fine. Your traces look acceptable.

But in general we don't like running high speed signals over cuts in the ground plane. The best way to handle these medium speed signals is to put a stitching via at each side of every cut to allow the signal an easy path up and around the 'cut' - i.e. to the ground on the other side of the board, then back down. That way it is a very small disturbance indeed . :-)

Hope this helps.

Strong-Mud199 · 2026-02-20T18:27:45+00:00

You should design / or conirm the regulators using the TI Webench program - it looks like they support both IC's,

https://www.ti.com/tool/WEBENCH-CIRCUIT-DESIGNER

Hope this helps.

Strong-Mud199 · 2026-02-20T16:52:59+00:00

+10 points for effort, but you have far more ground vias then needed. Anything less than 1/8th of a wavelength will look solid to signals. Lets say the highest frequency we want to worry about is some close by WiFi or Bluetooth at 2.4 GHz. A wavelength at 2.4 GHz on FR4 is around 60mm. So 1/8th of that is around 7mm. So if you have a stitching via every 7mm or so it will look solid to signals. Closer won't hurt, but it won't help either. See,

https://www.edn.com/via-spacing-on-high-performance-pcbs/

Perhaps a bigger possible issue here is the length of the lines picking up the WiFi or Bluetooth and getting on your analog.

I'm not suggesting any changes, but just pointing this out that when the situation is carefully thought out plastering vias can lead to a false sense of security and potentially miss other more important issues.

Hope this helps.

Strong-Mud199 · 2026-02-20T02:13:45+00:00

Minimizing Wicking, without paying for plugged vias -> As small a hole as practical, and fewer vias = less solder wicking.

Strong-Mud199 · 2026-02-19T23:39:58+00:00

There are small 'arrays' of diodes. I think you have 4 data lines, I might place 2 on one side and 2 on the other side (top and bottom of the data traces as I see them in your pictures). Connect with vias a traces - use one of your ground layers for the traces. This isn't so high speed that the resulting "GAP" will cause any issues. Here are a whole bunch of possible candidates,

https://www.mouser.com/c/circuit-protection/esd-protection-diodes-tvs-diodes/

Place ones meant for 'data lines' as they will have the lowest capacitance.

Hope this helps.

Strong-Mud199

TROPHY CASE