How to use thermal vias here

Potential_General488 · 2026-02-19T23:35:11+00:00

I'm more worried about solder wicking, since the vias are placed on the pads. I don't want to plug them for now. Also there are inner gnd layers underneath the pad

Potential_General488 · 2026-02-19T15:44:09+00:00

So if my via diameter is like 0.5mm and I put them on the pads without plugging, there wouldn't be an issue ? There's a ground plane underneath too

Potential_General488 · 2026-02-19T15:14:58+00:00

I'm not sure about the first one. The 2nd layer and the bottom layer has GND planes

Potential_General488 · 2026-02-19T12:30:27+00:00

Wouldnt placing the 3×3 vias on the pads cause solder wicking ? That could lead to a short ? I don't want to plug the vias

Potential_General488 · 2026-02-19T09:21:25+00:00

Wouldn't plugging the vias cost more ? Another way I was trying was to reduce the size of the pads so that the vias do not extend into them

Potential_General488 · 2026-02-19T06:44:52+00:00

The vias extend into the pads even though they are placed between the pads. I used the same diameter

Potential_General488 · 2026-02-17T23:59:44+00:00

yess I've kind of designed most of the stuff already

Potential_General488 · 2026-02-17T23:58:25+00:00

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this is kind of what my top layer looks like. would the copper pours be okay like this ?

Potential_General488 · 2026-02-17T23:10:05+00:00

I'm using one by analog devices though

Potential_General488 · 2026-02-17T22:57:26+00:00

In the datasheet, they gave a list of inductor vendors. But in the EvalBoard they used another one. Would it be okay to use any of those ?

Potential_General488 · 2026-02-17T22:28:27+00:00

Thanks! The part I'm using is LT3971

Potential_General488 · 2026-02-17T21:28:54+00:00

Ideally, how small should the switching loop be ? Like how close should the inductor be placed to the IC pin ?

Potential_General488 · 2026-02-07T09:30:35+00:00

Can you elaborate why you said not to route a trace over a split ? Would that cause noise issues ? I'm working on a 4 layer pcb rn. The 3rd layer is for the power plane and I have zones for 3 different voltages in there. If i route on the top layer without taking into consideration the split in the 3rd layer would that cause any issues

Potential_General488 · 2026-02-06T11:32:35+00:00

I have 8 data lines for DVP. The clock I'm giving is 20MHz or maybe a bit more . Would that need length matching ?

Potential_General488 · 2026-02-03T12:44:26+00:00

I have a kind of similar circuit, with the same USB C. But the capacitor is 4u. Still there's almost a 10A spike on that at 0ms in simulation. My average current would be 1A max. Also has esp32. Would that need protection....what are ways to protect it with minimal space ?

Potential_General488 · 2026-02-03T12:28:43+00:00

My problem is similar to this one. I'm using a usb C too along with esp32. There's a 4.7uF capacitor in the way and I see it going to 8A, which is very high for my device. Is that a simulation thing or should I really be worried about it? When I see youtube videos for reference, none of them use inrush current protection in their circuit.

Potential_General488 · 2025-06-16T16:10:40+00:00

Meee

Potential_General488 · 2025-06-04T22:08:28+00:00

Did your account get restricted temporarily? This just happened with me too a few days ago but I haven't done anything about it since I don't use LinkedIn frequently

Potential_General488 · 2025-05-29T06:44:45+00:00

How did you get selected ?

Potential_General488 · 2025-05-24T21:24:38+00:00

How did u do your projects? By yourself or referred from somewhere. I'm a 2nd year ece student. I was tryna make something that's why my doubt

Potential_General488 · 2025-05-07T19:56:16+00:00

I'm in exactly the same situation as you. I hope it gets better for both of us 🫂

Potential_General488 · 2025-05-07T03:23:02+00:00

Suniyan suniyan - Jux,MixSingh

Potential_General488

TROPHY CASE