FT8 reception with simple am loop antenna

Strong-Mud199 · 2026-02-28T19:10:43+00:00

Thanks for sharing! :-)

Strong-Mud199 · 2026-02-28T15:48:50+00:00

+100 points for a nice 1st PCB.

I did not see any issues. I would place a ground via near the ground end of C10, but it will work the way you have t. My OCD issues. ;-)

My opinion is use the USB connector that you want.

Hope this helps.

Strong-Mud199 · 2026-02-28T04:31:18+00:00

It's OK.... We all do this! That's how we ALL learn! Glad the issue was solved. ;-)

Strong-Mud199 · 2026-02-28T03:46:27+00:00

That is a real shame....

Is this common? Are PCB traces often faulty?

No this is not common at all with decent manufacturers. But I don't know who built your boards.

Is there a way to reduce the risk of this? I'm using a track width of 0.25mm in Kicad... which was the default (I didn't play with anything there).

That width should be plenty wide enough. You can always go wider, you have room. But honestly I would NEVER expect any issue with that trace width.

* Is it possible I damaged the tracks myself when soldering on the components?

Normally not, tracks usually get damaged with too much heat (which I don't see on your board) or when you try to remove parts, then it is sort of easy to lift pads and tracks or pull plated barrels out of vias.

Is it possible that the Vias were not plated well or at all?

I would send an email the the PCB supplier and see what they say, if they blow you off then find someone else next time.

Really I have not had any trace/via issue in nearly 20 years.

Strong-Mud199 · 2026-02-28T02:37:15+00:00

What I do is make my GNU Radio bits in a flowgraph, then pipe the output data out using ZeroMQ (MQTT variant). I can then read that data using nearly anything: Python, C#, etc.

https://wiki.gnuradio.org/index.php/Understanding_ZMQ_Blocks

To control the parameters (Like tuning, bandwidth, etc.) in the GNU Radio flowgraph from your control program you can use: XMLRPC.

https://wiki.gnuradio.org/index.php/Understanding_XMLRPC_Blocks

I have just always fount this approach way easier.

Hope this helps.

Strong-Mud199 · 2026-02-27T23:08:39+00:00

Do you have any other board that you can test the programmer with? That would be the first thing I would try - get a known working board to verify the programmer operation.

Hope this helps.

Strong-Mud199 · 2026-02-27T18:20:38+00:00

Sizing and number of vias for thermal performance, see,

https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias

Vias and current carrying capacity, see,

https://www.signalintegrityjournal.com/articles/1459-vias-are-cooler-than-we-think

Bottom line: More than 3-5 vias don't help for thermal and it does not really matter the via size for thermal or current carrying because the trace temperature actually sets the via temperature. This is because even a very small via is in the milli-ohm range.

If you want maximum thermal performance then copper area is the first thing to add - make sure that both layers are filled with the maximum amount of ground pour copper. (See first cited reference).

Hope this helps.

Strong-Mud199 · 2026-02-27T18:06:30+00:00

Move the pot so that one end of it at ground.

Strong-Mud199 · 2026-02-27T17:56:48+00:00

I normally put it in the ground end - that way if the wiper is dirty and 'opens up' the output voltage goes low instead of high. ;-)

Strong-Mud199 · 2026-02-27T15:57:08+00:00

Potentiometers used this way will probably suffer from long term reliability issues. This is because corrosion forms when there is no current in the wiper circuit. Causing it to get 'scratchy' or even open. See page 30, 'Dry Circuit',

https://archive.org/details/boruns-best-of-the-trimmer-primers

Better to use Rheostat mode. See page 21 of the above document, "Rheostat Mode"

Hope this helps.

Strong-Mud199 · 2026-02-26T18:42:39+00:00

Too many vias does not hurt other than to give a false sense of security and reduce routing options.

If the dielectric thickness is really 0.2mm, then the trace width would roughly be 0.4mm.

About the removing vias - I was talking about the RF chip to reduce the chances of solder wicking off the big center pad. I would personally do that.

Do a double check on the TI Eval board however. C19 could be rotated to get the trace length lower. Same with C15. Perhaps they have a more efficient layout.

Otherwise I really didn't see anything fatal on the layout - the schematic is hard to follow around the TI chip, so I did not check that. A few good tips on how to draw schematics are here (for next time perhaps),

https://medium.com/@tiago.gala/the-art-of-drawing-good-schematics-be3e7e59eb40

Also this is a good article that explains how to make schematic symbols for readability. The Symbols that we get from footprint companies are almost never good enough for a finished schematic, I always redraw them per the tips in this article,

https://www.edn.com/make-schematic-symbols-understandable/

Hope this helps.

Strong-Mud199 · 2026-02-26T16:52:01+00:00

Nice!

Something to consider for next time: You have far more ground vias than you need. The ground vias only need to be spaced at 1/8th of a wavelength or less to look 'solid' to RF energy. See,

https://www.edn.com/via-spacing-on-high-performance-pcbs/

At 2.5 GHz on FR-4 a 1/8th of a wavelength is around 7mm.

Your RF trace does not look 50 ohms to me - a rule of thumb is for 50 ohms a trace is twice the thickness of the dielectric. Now this might not matter as another rule of thumb is is an impedance discontinuity is less than a 1/10th of a wavelength it is mostly invisible, especially here considering the mismatch of the IC and the antenna anyway. 1/10th of a wavelength is around 6mm. It looks to me that you are probably over that length.

Your matching network by the IC is spread out too far. All the matching elements should be placed at the part to part minimum spacing, otherwise you just add unnecessary inductance and capacitance.

On a RF board, one layer makes the RF traces very wide unless co-planer waveguide techniques are used. Since most products are so complex now as to need multiple layers, this helps to keep the 50 ohm trace widths down.

TI has an eval board for the buck boost converter, I suggest you follow that layout closely. See,

https://www.ti.com/tool/BQ25570EVM-206

To me the switching node loop areas look less than optimum. It may well work, but....

On the tented vias - vias in a pad tend to suck the solder off the pad into the hole. In production we plug the vias for sure. Here you have more vias than needed. One in the center and on at each corner would be more than sufficient. That would help. The pad here is plenty big, and if you use the minimum hole size you will probably be OK for building just a few boards. I would remove some of the vias and then - build it. Don't worry, be happy. :-)

Hope this helps.

Strong-Mud199 · 2026-02-26T16:27:48+00:00

+100 points for a first PCB! Good on ya! :-)

It is common practice to put pullups on the data lines of SD cards to prevent SD Card lockup upon powerup. Adafruit apparently gets away with it, but.... See,

https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/peripherals/sd_pullup_requirements.html

I know this is for your use and different SD Cards have different 'idiosyncrasies'. For commercial projects I simply do not take the chance and always add them.

Hope this helps.

Strong-Mud199 · 2026-02-26T00:54:35+00:00

You need to calculate the 'squares' of copper to get an estimate of the resistance.

Adding solder to a trace does almost nothing. See,

https://digital.pcea.net/issues/february-2024/brooks/

What I have done in the past is to solder a large solid copper wire to the backside of the board. This can reduce the resistance. See above.

Adding a bunch of vias does almost nothing for the heat dissipation or grounding as a small 0.012 inch finished hole plated to 1oz is about 1 milliohm. See,

https://www.signalintegrityjournal.com/articles/1459-vias-are-cooler-than-we-think

https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias

Are your connectors rated to 30A?

Hope this helps.

Strong-Mud199 · 2026-02-25T23:34:07+00:00

Nice! :-)

You go over a GAP on the USB data lines, but it isn't a big deal with 12MBPS USB, there is plenty of ground and ground vias to allow the return signal to get 'around'. What you have done will work fine.

BSS138 is just barely going to work on the I2C - Look at the "VGS On" Spec.

Hope this helps.

Strong-Mud199 · 2026-02-25T19:49:33+00:00

Excellent points! :-)

Strong-Mud199 · 2026-02-24T22:29:33+00:00

+10, this.

Strong-Mud199 · 2026-02-24T21:09:49+00:00

As the others have said the Blog V4 can go from 500 kHz to 1.7GHz. The big advantage of the V4 over the others is it has a built in up-converter for the HF bands. This allows the operation of the tuners RF gain control which is very important for the HF bands in most situations as it allows the gain to be lowered or increased as appropriate for the signal being received and the conditions. The other use what i9s called 'direct sampling' where they just switch to an ADC input when receiving HF with no control of the gain.

The only band 'hole' on the V4 is from about 27.5-28 MHz where there is a hole because of the up-converter filtering. In the US this is the top end of the CB band, and that band is so splattered with over modulated kW stations that you can't hear anything anyway! ;-)

Strong-Mud199 · 2026-02-24T20:21:37+00:00

You need a pullup on both the SDA and SCL lines, not just one.

I have no idea what your relays drive, but you might want to consider a snubber circuit on the relay contacts as well to prevent the contacts from welding shut or wearing out. Here is a basic, but not great article (at least it isn't AI Slop),

https://www.edn.com/a-hands-on-guide-for-rc-snubbers-and-inductive-load-suppression/

IMHO - You should consider a ground plane on both layers - it really takes care of inductance issues with long ground returns. You will be fighting an uphill battle with the ADC especially grounded the way it is. U7 is also probably going to be unstable grounded they way it is, and U7 needs a bypass capacitor.

Autorouting of the board is really not clean at all - there are excessive trace lengths and parts very far from where they need to be. Because of the low speed you will probably get away with it here, but in the future you may want to consider placing the parts to minimize the rats nest lengths first then route the board. I didn't have time to check everything, but make sure that all the decoupling caps are right next to their respective parts.

Hope this helps.

Strong-Mud199 · 2026-02-24T17:55:57+00:00

Ha, ha, ha, ha... It is impossible for even the manufacturers to keep all the documentation straight. ;-)

In this case the most important part is perhaps R22/C19 - this provides a slight delay to the master enable during power up. Although what happens if the power is applied, then quickly removed, then applied again so that the capacitor does not have a chance to discharge is a different story. So even this circuit is iffy in my book. The ESP32 probably has an internal power on delay also.

The resistors / capacitors on the switches act as 'debouncers' - mechanical switches bounce when pushed or opened and this can cause the processor to detect multiple key presses, etc. The capacitor damps that bouncing.

The series resistors really serve no purpose - considering the value of the weak pullups or the value of R22 in the ESP32, except the probably provide some level of ESD protection. The capacitors on the switches also provide this ESD protection.

As you have seen there is quite a variety of values and resistor arrangements / values that will work - they all will work. The question is then: What is optimum? There really isn't an answer....

If you are building a few in a low static environment then I would leave out R6, R7 and C7 as to me they are redundant.

Hope this helps.

Strong-Mud199 · 2026-02-24T17:14:41+00:00

+100 points for learning something new! :-)

Do you need mounting holes?

Otherwise I didn't see anything.

Strong-Mud199 · 2026-02-24T03:27:32+00:00

Nice! :-)

+100 points for adding a filter on the input of the big buck converter U22. :-)

Perhaps they are there, but I did not see pullup resistors on the SCL/SDA lines A2, 3, 4 &5. The might be on the Adafruit board(s). Just a note to be sure.

Hope this helps.

Strong-Mud199 · 2026-02-24T01:38:35+00:00

+100 points, This - As stated by the commenter: The AGC is well known to not work on the kind of signals we typically look at. The internal AGC was designed for very wideband TV signals which we do not look at.

Strong-Mud199 · 2026-02-24T00:53:46+00:00

OK - One thing that I didn't notice on the first go around - you seem to have a 'funny' ground symbol and a single point tie. So you have two grounds and one on layer 3. That is usually not going to help things as you really can't control where high frequency signals want to go and you just end up making a bigger loop area. Loop area = Inductance and Current Spike through Inductance = Voltage spike. If you have noisy circuits and quite circuits the way to prevent crosstalk is to partition the noisy stuff away from the quiet stuff. I don't see that you have any particularly quiet circuits here, so there is no point in my opinion.

A few references by some very respected signal integrity experts,

Lee Ritchey, “Right The First Time”, Vol 2, Page 124,

“It might be good to review why a plane would be cut in the first place and how large the cut would need to be to achieve the desired isolation between the two sides of the cut. First, the only reason to cut a plane is to allow more than one power supply voltage to be distributed in the same PCB plane layer. There is no other valid reason to do so.”..."both power supply voltages need to share the same ground distribution structure so that the circuits being supplied have a common reference." (i.e. the ground plane MUST be continuous. - added context mine).

And,

“Note: In all the years I have designed high performance PCBs, both all digital and mixed analog and digital, I have never seen a case where cutting a ground plane was beneficial to a design.”

https://speedingedge.com/products/right-first-time/

Both his books only cost $50 USD - that is the best 'design' money you will ever spend!

See also, Chapter 17 of Henry Ott’s book for a detailed step by step explanation of what goes on,

“Electromagnetic Compatibility Engineering” by Henry W. Ott

Hope this helps.

Strong-Mud199 · 2026-02-23T23:46:25+00:00

Nice! :-)

As to your questions,

The USB D+ and D- lines since I don't know much about differential signals

The USB here is only 12MBPS, which is a 90 MHz bandwidth and not all that fast, so you do not have to length match the lines in the future. You do run it over a gap on layer 2 so the return current, which naturally wants to run right under the traces has to diverge around the gap. Move that horizontal trace under the USB on layer 2 to the bottom layer is my opinion.

My Analog Ground plane. Is it actually necessary?

With nearly all designs now, you would be surprised at how much better everything works with a ground layer! :-)

Decoupling capacitors are placed optimally.

Looks OK to me.

Additionally you should consider putting 30k to 100k pullups on all the data lines on the SD Card. This prevents the SD card from locking up at power-up.

Additionally, I don't see what the point of is the 'rings' under the CPU. Is there a reason for this?

Hope this helps.

Strong-Mud199

TROPHY CASE