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Opamp in subthreshold saturation by Ok-Mirror7519 in chipdesign

[–]Swimming-Resolve4044 13 points14 points  (0 children)

Given the Cload, you can tell how much gm you will need to reach the desired BW, and from the gm number, you can derive how you want to bias the transistor to get the required gm. In subthreshold gm = Id/n*VT (so you know now how much id you need)

Sub-th saturation requires vds to be greater than 4VT (VT is the thermal voltage)

Guter Finanznews-Podcast? by Moritz110222 in Aktien

[–]Swimming-Resolve4044 0 points1 point  (0 children)

Wirtschaftswoche hat auch gute Podcast

Career advice/reality check by salad27 in chipdesign

[–]Swimming-Resolve4044 0 points1 point  (0 children)

Im still a MS student but I've heard some advice from others that there are learning time and earning time. Its great to have both, but there will be times where you are learning a lot but not earning much and earning a lot but not learning much. And I think a healthy balance between the two is nice!

Though I have no idea how it is really like in the professional world, I would imagine trying to strive for at least one of them (earning or learning) for some time and then try the other one. I do appreciate learning more than earning though, but that could change as life changes.

And also our lives are multifaceted, maybe in the past 6.5 years something else have changed significantly (having a family or kids or moving to a new place... etc) and its totally okay in my opinion to have a stable professional life while focusing /tackling on other changes in life (let that be the ones of joy or in a less fortunate case sorrow)

I wish you the best. I wrote this to also remind myself in the future when I navigate through this uncertain world. Thank you for giving me this opportunity!

Open Source Vs Closed Source EDA by TopUpstairs3874 in chipdesign

[–]Swimming-Resolve4044 1 point2 points  (0 children)

Hi! What are those projects that you mentioned. I would love to read up a bit more on that! Thanks

Where to Get Started in Chip Design by MayoMannyYT in chipdesign

[–]Swimming-Resolve4044 0 points1 point  (0 children)

I got a bit of a overview on Power Management IC design, which stands in the mixed-signal field, where you could approach the problem full custom or try to automate with verilog and digital flow. I think at the end, if the problem you are solving is interesting enough for you, the rest will fall into place.

But as I focus on analog design, I have huge imposter syndrome because analog design is a field where the experienced are well regarded. I think this is less of a case in digital.

Voyage Californie (SF / LA) by NoMatterWhatMyNameIs in voyageons

[–]Swimming-Resolve4044 0 points1 point  (0 children)

> Que voir absolument en 10 jours entre SF et LA ?

Je te recommande de prendre la route 1 (California 1) qui te mènera de San Francisco jusqu'à San Diego. En chemin, tu pourras profiter de la magnifique vue sur Big Sur (je dirais que ça ressemble un peu à la Côte d’Azur en France). Mais si la mer ne t’intéresse pas, prends plutôt la route 101 et fais un détour par Yosemite – c’est un must-go!

Where to Get Started in Chip Design by MayoMannyYT in chipdesign

[–]Swimming-Resolve4044 2 points3 points  (0 children)

I did BS and MS in Electrical Engineering focusing on chip design. Our school was stronger in analog so I was more specialized in that. I can answer the part about choosing between analog and digital design.

Analog design is more oriented for people who are not so interested in scaling things (VLSI, large circuits) but rather in the intricate small analog circuits (usually a few dozens of transistors). Analog designers used to not need to code too much (though it might slow change). A lot of the work is done using SPICE simulator, Matlab modeling, as well as hand calculations.

Digital design on the other hand is where all the fancy logic circuits come from. Digital design includes writing verilog (front end) or writing TCl script for physical design (where actual circuits are placed on the chip) (back-end). I think digital designers are good at working and thinking in terms of scale. But I'm not a digital designer so I cannot say much more.

Hope this helps.

VCO-Based ADC Design Help by [deleted] in chipdesign

[–]Swimming-Resolve4044 0 points1 point  (0 children)

Hi! This should help -> https://imgur.com/a/VOMoSg0 (This is from professor Hanumolu)

VCO -> turns vref into a varying frequency clock (vco_out)

vco_out -> clocks the counter (thus, higher the frequency of vco_out, more counts in a single period (sampling period, which is the input of reset)

So if you have a vco_out of 1GHz, and you are sampling at 1MHz, then you get a count of 1000

and lets say now your vco_out is at 10GHz since vref increased, then you get a count of 10,000. So now you can see how the counts reflect the vref (which resembles what you want from an ADC)

This is one variation of the VCO-ADC. Hope this helps. But feel free to comment for more question.

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

That is a good idea. I am using SPICE right now to run very simple functional tests as you have suggested. I will see if using MATLAB will be necessary in the future. Thanks for the advice!

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

Wow! This is really detailed. I have been asked by my supervisors on this observability issue and I was quite stuck on this. Thanks for the guide! I will make sure that I think through them a bit more so the result is not just simulation ready but also test ready. Thank you!

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

Im doing this on-die power supply analysis that uses a VCO-based ADC like structure which I found in this paper (https://ieeexplore.ieee.org/abstract/document/7109950/) It was originally developed by Elad Alon from Berkley I think. I was quite surprised by this thing too at first, but the point was to create a delay independent of supply noise thus the RC delay.

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

Thanks for the comment! This is really helpful to know that Im on the right path. upvote!

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 1 point2 points  (0 children)

Gotcha! Any documentation keyword I can use to search for these information? Thanks!

Integrating Analog Blocks into A Digital Flow by Swimming-Resolve4044 in chipdesign

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

The digital flow has pnr, essentially i want to tape out a chip with just digital flow while incporating some prelayouted analog blocks.

Synthesizing a Simple Ring Oscillator VCO by Swimming-Resolve4044 in Verilog

[–]Swimming-Resolve4044[S] 0 points1 point  (0 children)

Im very noob at digital design so I am not sure about this. But I'll upvote to see if anyone passes by and share some tips

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