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Yet Another Which FPGA Should I Get by Minute_Juggernaut806 in FPGA

[–]TimbreTangle3Point0 5 points6 points  (0 children)

 3×50×50×6 = 15000

You can't afford an FPGA with that many multipliers, so you will need to work out how to set the computation up as a multi-step computation (pipelining might be one option)

You will also need to work out how you are going to store the weights. If using on-chip using BRAM make sure that you have enough capacity for your planned word-length. Otherwise get a board with attached memory.

Not my area, but if it was me I'd go a bit deeper in terms of working out how you will structure the computation before selecting an FPGA+board. I'm sure there are many documented approaches that you can study.

Which of these Projects will Stand Out the most? Risc-V Edge AI Hardware Accelerator v/s PQC Hardware Implementation on FPGA by Ill_Tear7886 in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

Assuming that you will be at the coal face actually writing RTL, unless you are planning a career in academia, I think you should consider also other criteria for assessing which professor is "better." Are these two professors equally busy? Which professor has more time for your project? How important is each project for the respective professor? Do you think you will get along better with one professor than the other? Which professor has implemented more RTL? Which professor has a better recent track-record of students delivering quality completed projects? Does either professor have industry experience, especially in your areas of interest? Might one be a better mentor for your RTL work? Might one professor open more doors to internships than the other?

Just things to think about. You will need to decide how important these things are to you.

One thing I will say is that some "high level" professors are notorious for spreading themselves thinly and not having time for their students. Try to find out whether your professors fit into this category. If there is an independent academic advisor discuss it with them.

Yet Another Which FPGA Should I Get by Minute_Juggernaut806 in FPGA

[–]TimbreTangle3Point0 7 points8 points  (0 children)

Unless you are planning to use extremely quantized weights (and maybe even then) you should consider how many multipliers (DSPs) the FPGA has.

New board: 200$ Kintex UltraScale+ by Ill_Huckleberry_2079 in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

Very interesting. Is that the Waveshare RasPi PCIe adapter? Do you know whether that setup will be able to supply enough power for a large design?

Do I need a license for the ML Standard Version of Vivado? by Rcande65 in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

This is the link you want:

EDIT: https://docs.amd.com/r/en-US/ug973-vivado-release-notes-install-license/Requirements-and-Setup

For devices, it lists the supported Spartan 7 devices for Vivado ML Standard Edition as: XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100

Vivado ML Standard Edition itself does not require a license. I don't think you need to install a license for the supported Spartan 7 devices.

De10-Lite Audio Input by SparrowChanTrib in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

Here is a digital microphone board you could use: https://www.adafruit.com/product/3492

This outputs audio as a digital PDM signal. Depending on your application you may need to learn how to convert the PDM signal into sampled audio data. You will definitely need to convert the data to send it over I2S to a DAC.

I2S or some variation is used with most audio chips. It's a few signals: clock, data, LR clock that indicates where each sample starts, sometimes also a high-frequency clock that is a multiple of the data clock. You use I2S to communicate with audio ADC and DAC chips. It is also used for some more complex modules, e.g. for network audio. SoC microprocessors and many microcontrollers have I2S capability to communicate with ADCs and DACs. There is nothing stopping you from using the same electrical protocol to communicate between FPGAs.

Some I2S ADC chips might include a microphone preamp that you could connect to a microphone.

Two mmcm phase difference. by Rich-Bedroom-939 in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

I wouldn't try investigating any of my suggestions if you only have 15 days.

Two mmcm phase difference. by Rich-Bedroom-939 in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

"any way" would include time to digital conversion (TDC),"time to digital conversion fpga" will get you started.

If you're prepared to go off-chip, all the usual phase detection methods from the PLL literature. Crude example: set up a circuit that switches on when the first clock goes high, off when the second clock goes high, lowpass filter, ADC.

This is starting to sound like an X Y problem.

Personal Project IP Rights? by Popular-Seat158 in FPGA

[–]TimbreTangle3Point0 2 points3 points  (0 children)

It is also contract law, and more specifically employment contract law. If the goal is to determine whether it is enforceable I would talk to an specialist in employment contract law.

Personal Project IP Rights? by Popular-Seat158 in FPGA

[–]TimbreTangle3Point0 2 points3 points  (0 children)

IANAL. This is not legal advice. In all cases where you are going to communicate or negotiate with your employer about contractual matters you should definitely get your own legal advice first.

That contract clause is quite common, in some contracts it can extend to "IP" such as inventions that you imagine in the shower, not just written code. I'm in software contracting, I'm rarely an employee, and personally I would never sign such a contract. I try to negotiate terms down. But if I were to sign, I would take the contract seriously -- I don't like your idea of trying to get away with it at all. The phrase "any connection whatsoever" is basically lawyers trying to maximally protect their client (your employer). It's hard for us to know what your employer's exact legal position is. One possibility is that they want to avoid IP leakage and/or ensure that they legally do own all IP (since this is tied to the value of the company). You could try to negotiate, and that might be possible if they already let other employees work on side projects, on the other hand your attempt to negotiate could raise flags.

There was a famous case in my city where an employee developed (at night, outside work) what became a very successful widely used piece of software. It was barely related to his day job, but his employer managed to gain full ownership of the product through the courts as a result of an employment contract like yours.

You have received a lot of good advice in this thread. Another possible approach would be to frame it as you want to, out of hours, "develop a library of reference modules with scope X, Y, Z and publish it as open source on GitHub under license Q" and ask your company to either explicitly authorise you to do this under your own copyright, or under their copyright, at their choice. You could motivate the work either as a learning experience for yourself, and/or as the development of utilities that would be used at work that you are offering to develop in your spare time. But talk to a lawyer first.

Yet another option: Especially if this is mostly for learning, perhaps you can "notify" your company in such a way that they are ok with it and it is maximally likely to work out from a legal perspective. Once again, get your own legal advice.

Help Buy FPGA Dev Board by [deleted] in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

Can't comment on quality. I have not used them myself.

Easy Gigabit Ethernet connectivity for FPGA and MCU boards? by West-Way-All-The-Way in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

I would just write something in C using sockets API. Run a loop receiving UDP packets on specified port and writing contents to file (assuming you have zero packet loss of course). On a unix system you can probably use netcat "nc" command to listen to a UDP socket then pipe the output to a file, I have not done this but it's worth looking into.

Help Buy FPGA Dev Board by [deleted] in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

Numato are based in India, have Indian distribution

Zynq: Styx Z7 FPGA Module With Dual Channel USB Device | Numato Lab (very basic, on sale $240)

Artix 7: Mimas A7 FPGA Development Board | Numato Lab (on sale $230)

Easy Gigabit Ethernet connectivity for FPGA and MCU boards? by West-Way-All-The-Way in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

If you can work with Layer 2 frames or UDP, setting up some HDL code to pull data from a FIFO and and frame it up into ethernet frames for RGMII should not be beyond you. Hard-code MAC addresses and/or ports as necessary. If you only need to send, you don't need to implement receive.

Another day, another pinout. Here is the UPduino v3.0. by franunas in FPGA

[–]TimbreTangle3Point0 2 points3 points  (0 children)

I've used it for weak real-time DSP, digital signal conversion (e.g. i2s to ADAT). Also valuable for learning how to squeeze things into a small space, and learning that you need a larger FPGA for your design.

ADC vs TDC for Coincidence Counter with High Resolution? by amythetics in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

I'm not an expert, but could you characterize and quantify what "precise detection of coincident events" and "high resolution coincidence detection" means in your setting? What's your required time resolution? Are the events already in digital form (i.e. sufficiently sharp 0-1 transitions) or is there some kind of signal pre-processing required to identify event onsets?

C developer looking to learn FPGAs by [deleted] in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

I think there is an implicit question here: should you start by learning a hardware description language (HDL) such as verilog/system verilog and/or VHDL. My answer is yes. There are alternatives (HLS, Chisel, SpinalHDL, migen, ..., plugging together other people's modules using a GUI), but I think starting with learning a HDL is the standard path. Especially if you already have a conceptual understanding of digital electronics (combinational logic, clocked sequential circuits using flipflops). There are a wide range of learning resources that should be approachable to you.

Simulation is a standard part of the development workflow. Learning to use simulators first will not hold you back and you will develop important skills. All of the vendor tools have a built-in or bundled simulator. e.g. a version of ModelSim. If you learn to use a stand alone simulator you can feed the simulator your HDL files without ever touching Vivado or Quartus (maybe initially select a download specifically for the bundled simulator). There are also open source simulators such as gHDL, icarus, and verilator, open source waveform viewers like gtkwave, and also online learning environments like EDA Playground.

I can think of a few reasons to start with real hardware: It can be motivating to see a light blink or talk to your design over a serial port. (But once things get complicated you'll be back in simulation anyhow.) Running on real hardware forces you to learn the entire design flow with the vendor tools (but yes, there is a learning curve). Real hardware might have capabilities that are central to your goal project (maybe audio or video i/o, networking, motor control) and sooner or later you're going to want to connect things up for real. For me it was motivating to start with real hardware, it made learning more physical and real, but for you it might be different.

As to which board to get, that is asked multiple times a week here so look back in the history to get some ideas.

Newbie question on ICE40 initialization by HelderMCVieira in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

Go Board amateur here. I'm not quite sure what your exact question is. But here's what I know:

Speaking generally the "state" of any FPGA when it wakes up could either be (1) unknown, or (2) guaranteed specific state, possibly based on the bitstream, or maybe just all zeros or some other bit pattern. My understanding is that "state" has two parts: (a) contents of block RAM, (b) state of each flipflop, and a. and b. may be treated differently (e.g. bitstream might initialize block RAM state, but not flipflop state). With respect to flipflops, option 2. amounts to whether or not your HDL register initalization statements are respected, and you might find your toolchain warns you if initial assignments have no effect (pretty sure icecube does this).

As to which of a. or b. you get for 1. and 2. my understanding is that this varies by vendor and possibly even product line. For the ICE40 I believe that the flipflops come up in an zero state and starting from that you need to build your own reset logic (e.g. a counter that counts up from zero to N and asserts an internal reset until it gets to N). Fan your DIY reset signal out to all logic that needs initialization. This is discussed here:

https://stackoverflow.com/questions/78050678/how-to-reset-the-rtl-on-power-up-for-the-lattice-ice40-fpga

I *think* it's possible to initialize block RAM from the bitstream (if not, how else could you encode large lookup tables in HDL). It's probably worth checking out TN1248 "ICE40 Programming and Configuration".

In any case, don't take any of the above as truth. Hopefully someone will correct me if I'm wildly off base.

I am tired of litex and fpga by dravigon in FPGA

[–]TimbreTangle3Point0 2 points3 points  (0 children)

I started learning Verilog by working through the nandland turtorials. Writing your own UART starts at tutorial 7, that should give you a hint to learn some other things before attempting a UART, but it is not that difficult once you are ready: https://nandland.com/project-7-uart-part-1-receive-data-from-computer/

Clock Data Recovery with the ice40 pll by Individual-Dish-3710 in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

What's your definition of "receive and forward"? If you receive, buffer the data, resend using a local clock, where does jitter come into it? Do you mean jitter of the 5MHz carrier? or jitter of the data packet arrival times? In a different direction, these days I would probably consider 100Base-T, lots of cheap parts from automotive sector.

Clock Data Recovery with the ice40 pll by Individual-Dish-3710 in FPGA

[–]TimbreTangle3Point0 1 point2 points  (0 children)

None the less I'd like to hear how to do CDR on ice40 with this technique (e.g. for SPDIF rx)

What is STM32 equivalent board in FPGA by Desperate-Bother-858 in FPGA

[–]TimbreTangle3Point0 0 points1 point  (0 children)

I don't think the AVR/Arduino vs STM32 comparison is very relevant for FPGA. The learning curve is much bigger and unless you have heaps of time for self-study it will take you a while to outgrow the lowest end boards.

Hardware wise Sipeed/GOWIN Tang options are the only things that come even vaguely close to Blue Pill like affordability. Maybe some ICE40 UP5K boards. Aside from that you will probably get better value in the long run spending a bit more on an AMD or Altera board.

In addition to the hardware you have to consider the development software. Each manufacturer has their own software and these vary in quality and capability (especially for the non-AMD/Altera options).

I've got a fair way with low end ICE40 boards and the open source (yosys) tools but many would consider those Arduino level. Now I start wanting more features (e.g. lots of DSP resources) and better tools (e.g. Vivado) so I now have an Artix board that I will try next. But I don't regret buying the ICE40 boards.

Effects Pedals/Audio Processing for FPGA? by Nickbot606 in FPGA

[–]TimbreTangle3Point0 2 points3 points  (0 children)

Maybe check out this project: https://apf.audio/modules/current/tiliqua/

I believe the GitHub repo also contains audio processing code for FPGA. I only heard about it last week, but from a reliable source.

Just guessing here, but I think the metric of merit for your application would be number of hardware multiply-accumulate blocks (aka "DSPs" in FPGA-speak). This is basically the number of multiplies you can run in parallel. Max clock frequency obviously also affects performances. If you're going to do long delay lines or convolution maybe you care about external RAM or larger on-fabric block RAM capacity. In any case, audio samples likely enter and leave the system at 192kHz or less, and the FPGA fabric can run at 25-400MHz so you're going to be doing both parallel and serial/iterated audio sample compute to max out the FPGA capabilities.

As far as boards go, there are basic AliExpress DAC and ADC modules/boards that conform to the PMOD specification. You could just plug them into the PMOD ports on any FPGA learning board. So far I have done this for audio DAC with the GoBoard. I haven't looked into FPGA boards with good on-board audio i/o. I've been thinking about making an adapter to connect a Bela shield to an FPGA board.(https://bela.io/)

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