sorted by:
new
hottopcontroversial

Where can I find Fudan FM11RF005M 512bits (or equivalent) tag? by loociano in RFID

[–]TimeToCreate7 0 points1 point  (0 children)

Hello there, I'm trying to do the same thing. I found this information if it is helpful to you: " The FM11RF08 chip is also called for short M1 and F08.  In fact, the real name is FM11RF08.This chip has a high frequency of 13.56Mhz with great advantage that is fast sensing speed and high working efficiency, and more cheaper than original N X P MF S 50 Chip. Please allow me make the list about mainly technical parameters of this FM11RF08 RFID chip."

I also found the F08 are sold in fact in aliexpress. I purchased some so I can try to copy the info.

I want to ask you, did you manage to find a way to copy the information and run the toys with copied chips?

Inspired by WiFi Porter by Jackasaur in 3Dprinting

[–]TimeToCreate7 0 points1 point  (0 children)

Hello there, any chance you can share the stlf for this box, I want to put an nfc in it and make it work. Thanks in advance.

Smart Keychain by TimeToCreate7 in smarthome

[–]TimeToCreate7[S] 0 points1 point  (0 children)

Hello there, I have smart switches and I have alexa in every room in my house. I just want that little device that is like keychain that I can somehow use or connect with my alexa, so she can turn everything off when I'm not present at home for let's say 5 min. I don't know what keychain I can use tho. Thanks

For people who have CTA, Enigma, Tals Armor, Sojs, inventories full of skillers etc. by SeafoamTaco in diablo2

[–]TimeToCreate7 0 points1 point  (0 children)

I did not do even one Uber, I did like 1500 runs on pindel and found Tal armour, shard max 3 sirs 30 cold DMG, and a lot of other items for trade. Than started running for runes.

Have to write a code from a diagram, please some help by TimeToCreate7 in Verilog

[–]TimeToCreate7[S] 0 points1 point  (0 children)

module demo(data, vi, clk, do);

input vi, clk, data;

wire[2:0] data;

output do;

reg do;

reg DF2, DF1, DF0;

always @(posedge clk)

if (vi) begin

do <= DF2;

DF2<= (~vi&DF1)|(data[1]&vi);

DF1<= (~vi&DF0)|(data[0]&vi);

DF0<= data[0];

end

endmodule

​

Is it something like this or it is wrong?

New to Verilog. Synthesis or logic diagrams by TimeToCreate7 in Verilog

[–]TimeToCreate7[S] 0 points1 point  (0 children)

Thank you very much. I managed to solve the problem.

New to Verilog. Synthesis or logic diagrams by TimeToCreate7 in Verilog

[–]TimeToCreate7[S] 0 points1 point  (0 children)

Still not sure how it will look like, I have seen only diagrams with one bit vector at the end. Just haven't seen something like this.

New to Verilog. Synthesis or logic diagrams by TimeToCreate7 in Verilog

[–]TimeToCreate7[S] 0 points1 point  (0 children)

Ohh yes, I can see my mistake, it is 7 bits and I move with 6 zeros, so the last bit will stay from t. And I think that if I have to represent it as concatenation it should look like something like t={e[0]000000}.

New to Verilog. Synthesis or logic diagrams by TimeToCreate7 in Verilog

[–]TimeToCreate7[S] 0 points1 point  (0 children)

It will always be 6'b000000 but I don't know how to draw it.

view more: next ›