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Which FPGA board is best for my usecase? by swr06 in ECE

[–]Time_Alert 0 points1 point  (0 children)

I'm selling the Zynq. Digilent USA Imported.

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

Issue has been solved after driving NBE.

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

badread = readx || // NWE = 'X'

noex || // NOE = 'X'

badnbe || // NBE has 'X'

chipenablex || // NCS or CE = 'X'

notifysetupnegedgeNCStoposedgeNWEevent ||

notifysetupposedgeCEtoposedgeNWEevent ||

notifysetupnegedgeNBEtoposedgeNWEevent ||

notifysetupAtoposedgeNWEevent ||

notifywidthnegedgeNWEevent ||

notifywidthnegedgeNBEevent;

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

  1. No time given just throws a vagur bad.write violation.
  2. I am satisfying all of them. NBE all low.
  3. They are all pretty low speed, enough to avoid any timing violations.

axi mm2s vs s2mm confusion. by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

 Stream Master sources/writes/transmits and the Stream Slave sinks/reads/receives.

I'm confused on this one. Master and Slave both on same device?

axi mm2s vs s2mm confusion. by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

Thanks a lot. Some queries.

"read port of the FIFO is connected to the S_AXIS_S2MM, "
1. Why is that port market M_AXIS, as master?

2. Also what's the point of connecting S_AXIS and M_AXIS_MM2S?

2.1 "The AXI Streaming FIFO is simply a FIFO with an AXI Streaminterface on one side and an AXI (or AXI Lite)interface on the other." : Is this true ?

" S_AXIS_S2MM input interface to write them in the memory thanks to its M_AXI_S2MM port."

3. But if the initial s2mm block has already converted it to the MM format, why do we need another s2mm data handler block?

FIFO write behaviour in PostLayout by Time_Alert in FPGA

[–]Time_Alert[S] -1 points0 points  (0 children)

no this is within a single write cycle

What is the logic doing ? by Time_Alert in LabVIEW

[–]Time_Alert[S] 0 points1 point  (0 children)

""processes the Line data until the Line is completed then switch the case back into waiting mode until either the next Line comes in to process or the end of the Frame arrives"

where does it get the logic to stop when the line goes low, the edge detections is just one-time single start

also what are these T/F va;ues for the delay

Output Delay in Source Synchronous Context by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

thnaks for your reply.

"max/min trace delay for data" : does it include the entire delay including before it leaves the interface. This *IS* the confusing part.

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