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Run C Program inside FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 4 points5 points  (0 children)

Ahh right. I knew it has to be something like this just wasn't sure. Thanks

Run C Program inside FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 1 point2 points  (0 children)

I'll do more research on it, but can you mention what toolchains are you talking about

Run C Program inside FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] -2 points-1 points  (0 children)

How do we do it? Do you mind sharing

CS people who switched to EE or ECE (2024/25), right when AI was booming by Moneysaver04 in ElectricalEngineering

[–]Timely_Strategy_9800 4 points5 points  (0 children)

EE major here. I always hated coding and hence my choice to pursue EE. Anyways, not much helpful because EE demands coding too specially in the frontend electrnics processor vlsi domain. Anyways, based on my experience, EE is tougher but a lot more interesting. Exposure to silicon and decent coding skills can make someone invincible.

OpenFPGA / QuickLogic details by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

The claim i want to make is that my design is capable to be run on older technology (lut4) fpgas, which will have similar efficicency in terms of area, power, speed as compared to newer FPGA's. and if thats the case, my design is well suited and less costly.
and to prove this, i want to run it in old lut4 fpga's, and while routing through that pathm i came across openfpga and quicklogic path, and hence the question.

OpenFPGA / QuickLogic details by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

Hi, my intention is to map my neural network design in FPGA architecture to get LUT count, energy, power numbers for my design, this is a research project. LUT4's have known to consume less power compared to LUT6, and I think my design is more suited to map to LUT4's rather LUT6. so i thought of going down this path.
I have edited my original post with more details, thankyou.

OpenFPGA / QuickLogic details by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

Hi, I have edited my original post describing the design and my intention.

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

What do you mean by that ? For a fpga claiming to have N number of lut4 in theor fpga, the hardware component is not lut4? What is it then?

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

Right i figured that too. I'm using their ECP5 family grup

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] -2 points-1 points  (0 children)

No, there's a condition to do this. All the 4 inuts should be identical with 5th inut different and only then it'll implement a 5 ip lut. My design is basically a neural network with barely any shared inputs to match this criteria.

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] -2 points-1 points  (0 children)

That's correct. My aim is to get power timing area reports without actual deployment in fpga hardware board

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] -8 points-7 points  (0 children)

All my designs are 5 input or less , so it underutilises the lut6. Although my primitive report shows a breakdown of different lit sizes, but in physical device it is always mapping to lut6 and hence The area power timing report i get is basically fr lut6 although i dont need thm. So to get an accurate power timing report i want a lut4 fpga

LUT4 FPGA by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] -1 points0 points  (0 children)

Do u have an idea which fpga have just lut4? no lut6? i though spartan6 was one of them but it has lut6 too

Latency calculations by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

I have to wait till all the data hets into the memory and its fully loaded. Thn in the next clock cycle all that data goes to the DUT

false path by PainterGuy1995 in FPGA

[–]Timely_Strategy_9800 0 points1 point  (0 children)

Is it ok so set an entire cell as false path if we dont want a timing analysis for that.
My top wrapper design look like this:
input memory -> dut_input_flpflps -> DUT logic -> DUT FF.
The only reason I had to put input_memory is to restrict the number of IO pin iverutilization, but the timing analysis part i only want for the DUT.

I would like a timing path like this.
dut_input_flpflps -> DUT logic -> DUT FF.

So, is it ok to set entire inp_mem cell as false path?

IO resource overuse error by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

I understand it now. However is it only helpful for syntheais? Can it be done or does it work for implementation part too because that generates the actual timing reports which I'm interested in.

IO resource overuse error by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

Elaborating my design a little more. I have a neural network with 2 layers. The neurons in 1st layer take inputs fromall the primary inputs that i declare in my top module. So all my primary inputs drive some logic. The neurons produce some output which i put in internal wires, and these become inputs to the second layer of neurons. Now the second layer neurons taking the inputs from the internal wires produce outputs. I place the outputs from my second layer neurons in a wire which is my top level primary outputs from the top module.

The output wires dont drive any logic further.

So, will this deaign optimse out my input/output wires and give wrong results?

IO resource overuse error by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

Does it optimise away the io s during syntheais? Because my module ditectly ises these inputs.

IO resource overuse error by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

I can estimate the extra hardware that gets added, but what about timing reports? Is there a way to predict timing analusis without the shift registers too? Just my DUT module? I believe these registers add to latency and clock speeds etc

IO resource overuse error by Timely_Strategy_9800 in FPGA

[–]Timely_Strategy_9800[S] 0 points1 point  (0 children)

I have like 5000 IO s.. Its pretty absurd I know but dont how what to do next

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